公开(公告)号：US20250112603A1

公开(公告)日：2025-04-03

申请号：US18374696

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Ashoke RAVI ,  Ofir DEGANI ,  Sashank KRISHNAMURTHY ,  Soumya GUPTA

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/22

Abstract: An amplifier structure may include a first amplifier substructure having a first amplifier and a first filter structure and provide a first high frequency output signal and a first low frequency output signal having a frequency lower than a frequency of the first high frequency output signal. It may include a second amplifier substructure having a second amplifier and a second filter structure and provide a second high frequency output signal and a second low frequency output signal having a frequency lower than the frequency of the second high frequency output signal. It may include a first combination node configured to receive the first high frequency output signal and the second low frequency output signal and to provide a first amplified signal, and a second combination node configured to receive the first low frequency output signal and the second high frequency output signal and to provide a second amplified signal.

公开(公告)号：US20240223416A1

公开(公告)日：2024-07-04

申请号：US18147736

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Hossein ALAVI ,  Elan BANIN ,  Ofir DEGANI ,  Ashoke RAVI

IPC: H04L27/00 ,  H04L27/26

CPC classification number: H04L27/0014 ,  H04L27/2657 ,  H04L2027/0016 ,  H04L2027/0026

Abstract: A system includes a processor configured to determine a frequency offset between a first local oscillator and a second local oscillator using a combined radio signal received at a first transceiver circuit; wherein the combined radio signal comprises a first signal transmitted by the first transceiver circuit and a second signal transmitted by a second transceiver circuit.

公开(公告)号：US20230299796A1

公开(公告)日：2023-09-21

申请号：US17695868

申请日：2022-03-16

Applicant: Intel Corporation

Inventor： Evgeny SHUMAKER ,  Run LEVINGER ,  Ofir DEGANI

IPC: H04B1/00 ,  H04B1/04

CPC classification number: H04B1/0014 ,  H04B1/0078 ,  H04B1/0082 ,  H04B1/0483

Abstract: A system may include a digital front end (DFE). The DFE may be configured to generate a command signal. The system may also include a sweeper. The sweeper may be configured to generate an intermediate in-phase signal, an intermediate quadrature signal, and a LO signal based on the command signal. In addition, the system may include a mixer. The mixer may be configured to generate a mixed in-phase signal based on the intermediate in-phase signal and the LO signal. The mixer may also be configured to generate a mixed quadrature signal based on the intermediate quadrature signal and the LO signal. Further, the system may include an amplifier. The amplifier may be configured to generate an in-phase signal based on the mixed in-phase signal and an amplification setting. The amplifier may also be configured to generate a quadrature signal based on the mixed quadrature signal and the amplification setting.

公开(公告)号：US20230093115A1

公开(公告)日：2023-03-23

申请号：US17482480

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Assaf BEN-BASSAT ,  Elan BANIN ,  Alaa BEIDAS ,  Ofir DEGANI ,  Ashoke RAVI

IPC: G06N3/063 ,  G06N3/04 ,  H03K3/037

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable and frequency-controllable oscillator that is configured to generate an oscillator signal. The spiking neuron may further include a spike signal detector that is configured to generate spike detection signals in response to detection of input spike signals. The spike signal detector may generate the spike detection signals based on the oscillator signal. The spiking neuron may further include a neuron structure that is configured to provide an output spike signal based on the spike detection signals and the oscillator signal.

公开(公告)号：US20220029650A1

公开(公告)日：2022-01-27

申请号：US16936456

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Ofir DEGANI ,  Rotem BANIN ,  Shahar GROSS

IPC: H04B1/04 ,  H04B7/10

Abstract: A transmitter for generating a radio frequency, RF, transmit signal is provided. The transmitter includes signal generation circuitry configured to generate, based on a sequence of first control words each indicating a respective frequency shift with respect to a target frequency of the RF transmit signal, a RF carrier signal with sequentially varying frequency over time in order to frequency spread the RF transmit signal. Further, the transmitter includes modulation circuitry configured to generate the RF transmit signal by modulating the RF carrier signal with a modulation control signal. The transmitter additionally includes modification circuitry configured to generate the modulation control signal by modifying, based on the sequence of first control words, phase information of a baseband signal bearing information to be transmitted or phase information of a signal derived from the baseband signal in order to frequency de-spread the RF transmit signal.

公开(公告)号：US20250167818A1

公开(公告)日：2025-05-22

申请号：US18655458

申请日：2024-05-06

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Eytan MANN ,  Rotem BANIN ,  Ronen GERNIZKY ,  Ofir DEGANI ,  Igal KUSHNIR ,  Shahar PORAT ,  Amir RUBIN ,  Vladimir VOLOKITIN ,  Elinor KASHANI ,  Dmitry FELSENSTEIN ,  Ayal ESHKOLI ,  Tal DAVIDSON ,  Eng Hun OOI ,  Yossi TSFATI ,  Ran SHIMON

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20240056120A1

公开(公告)日：2024-02-15

申请号：US17819329

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Sashank KRISHNAMURTHY ,  Ofir DEGANI ,  Ashoke RAVI

IPC: H04B1/525 ,  H04B1/00 ,  H04B1/30

CPC classification number: H04B1/525 ,  H04B1/0078 ,  H04B1/30 ,  H04B2001/307

Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.

公开(公告)号：US20240048351A1

公开(公告)日：2024-02-08

申请号：US17641830

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashoke RAVI ,  Ronen KRONFELD ,  Ofir DEGANI

IPC: H04L7/033

CPC classification number: H04L7/0331

Abstract: A radio-frequency integrated circuit (RFIC) configured to generate a synthesized clock includes a phase locked loop (PLL) configured to divide down a clock to a non-harmonic frequency; a plurality of multi-phase injection locked clock multipliers (ILCM) directly connected to a plurality of transceiver chains; wherein the PLL is further configured to distribute a divided down clock to at least one of the plurality of multi-phase ILCMs; wherein the plurality of multiphase ILCMs are configured to select a phase of and multiply the divided down clock to synthesize a desired harmonic frequency of the clock and suppress an undesired harmonic frequency of the clock.

公开(公告)号：US20230209282A1

公开(公告)日：2023-06-29

申请号：US17560320

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： David BIRNBAUM ,  Ofir DEGANI ,  Arnaud PIERRES ,  Oren HAGGAI ,  Amy CHEN ,  Revital ALMAGOR ,  Darryl ADAMS

IPC: H04R25/00

CPC classification number: H04R25/507 ,  H04R25/70 ,  H04R25/554 ,  H04R2225/55

Abstract: A method for operating a hearing aid system, the method including: providing an audio stream from a first communication device to a first terminal hearing device through a first wireless communication link, and wherein the audio stream is based on a personalized audibility feature of a predetermined user and an audio reproduction feature of the terminal hearing device; set up a second wireless communication link between the first terminal hearing device and a second communication device; providing the second audio stream through the second wireless communication link, and terminating at least the audio stream of the first communication link.

公开(公告)号：US20230100670A1

公开(公告)日：2023-03-30

申请号：US17483880

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Alaa BEIDAS ,  Elan BANIN ,  Assaf BEN-BASSAT ,  Ofir DEGANI ,  Ashoke RAVI

IPC: G06N3/04 ,  G06N3/063

Abstract: Spiking neuron circuits and methods are provided in this disclosure. A spiking neuron may include a triggerable oscillator configured to generate an oscillator signal. The spiking neuron may further include a circuit configured to obtain an integration value based on received input spike signals. The spiking neuron may further include a leakage circuit configured to obtain a leakage value based on the oscillator signal. The spiking neuron may further include an oscillator activator configured to activate or deactivate the triggerable oscillator based on the leakage value and the integration value.