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    2-D gather instruction and a 2-D cache
    2.
    发明授权
    2-D gather instruction and a 2-D cache 有权

    公开(公告)号：US09727476B2

    公开(公告)日：2017-08-08

    申请号：US14635403

    申请日：2015-03-02

    Applicant: Intel Corporation

    Inventor： Boris Ginzburg ,  Oleg Margulis

    IPC: G09G5/36 ,  G06F12/0875 ,  G06T1/60

    CPC classification number: G06F12/0875 ,  G06F2212/452 ,  G06T1/60

    Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

    PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTION CONVERSION MODULES FOR INSTRUCTIONS WITH COMPACT INSTRUCTION ENCODINGS
    7.
    发明申请
    PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTION CONVERSION MODULES FOR INSTRUCTIONS WITH COMPACT INSTRUCTION ENCODINGS 审中-公开

    公开(公告)号：US20180081684A1

    公开(公告)日：2018-03-22

    申请号：US15273163

    申请日：2016-09-22

    Applicant: Intel Corporation

    Inventor： Ching-Tsun Chou ,  Oleg Margulis ,  Tyler N. Sondag

    IPC: G06F9/30

    Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.

    BINARY TRANSLATION SUPPORT USING PROCESSOR INSTRUCTION PREFIXES
    8.
    发明申请
    BINARY TRANSLATION SUPPORT USING PROCESSOR INSTRUCTION PREFIXES 审中-公开

    公开(公告)号：US20170192788A1

    公开(公告)日：2017-07-06

    申请号：US14988298

    申请日：2016-01-05

    Applicant: Intel Corporation

    Inventor： Oleg Margulis ,  Jason M. Agron ,  Tyler N. Sondag

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/4552

    Abstract: A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix referencing an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.

    Eliminating redundant stores using a protection designator and a clear designator
    9.
    发明授权
    Eliminating redundant stores using a protection designator and a clear designator 有权

    公开(公告)号：US10540178B2

    公开(公告)日：2020-01-21

    申请号：US15265587

    申请日：2016-09-14

    Applicant: Intel Corporation

    Inventor： Vineeth Mekkat ,  Youfeng Wu ,  Sebastian Winkel ,  Oleg Margulis

    IPC: G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

    Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

    Instruction and Logic for Dynamic Store Elimination
    10.
    发明申请
    Instruction and Logic for Dynamic Store Elimination 审中-公开

    公开(公告)号：US20180074827A1

    公开(公告)日：2018-03-15

    申请号：US15265587

    申请日：2016-09-14

    Applicant: Intel Corporation

    Inventor： Vineeth Mekkat ,  Youfeng Wu ,  Sebastian Winkel ,  Oleg Margulis

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

    Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

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