公开(公告)号：US09880935B2

公开(公告)日：2018-01-30

申请号：US14222792

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC: G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

CPC classification number: G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US10248568B2

公开(公告)日：2019-04-02

申请号：US15879030

申请日：2018-01-24

Applicant: Intel Corporation

Inventor： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC: G06F12/08 ,  G06F12/12 ,  G06F13/28 ,  G06F12/084 ,  G06F12/122

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US20180165193A1

公开(公告)日：2018-06-14

申请号：US15879030

申请日：2018-01-24

Applicant: Intel Corporation

Inventor： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC: G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC classification number: G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

公开(公告)号：US20230217253A1

公开(公告)日：2023-07-06

申请号：US17922280

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed ,  Lokpraveen Mosur ,  Neelam Chandwani ,  Pinkesh Shah ,  Rajesh Gadiyar ,  Shrikant M. Shah ,  Uzair Qureshi

IPC: H04W12/125 ,  G06F9/50

CPC classification number: H04W12/125 ,  G06F9/505

Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

公开(公告)号：US20190188136A1

公开(公告)日：2019-06-20

申请号：US16281941

申请日：2019-02-21

Applicant: Intel Corporation

Inventor： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

IPC: G06F12/084 ,  G06F13/28 ,  G06F12/122

CPC classification number: G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

Abstract: A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.