公开(公告)号：US20230099540A1

公开(公告)日：2023-03-30

申请号：US17485294

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sarah ATANASOV ,  Rahul RAMAMURTHY ,  Seung Hoon SUNG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a semiconductor device comprises a sub-fin. In an embodiment, the sub-fin comprises a semiconductor material. In an embodiment, a channel is above the sub-fin, where the channel is physically detached from the sub-fin. In an embodiment a first layer is over the sub-fin, and a second layer is over the first layer. In an embodiment, the second layer is different than the first layer.

公开(公告)号：US20230097736A1

公开(公告)日：2023-03-30

申请号：US17485308

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Jason PECK ,  Nafees A. KABIR ,  Sarah ATANASOV

IPC: H01L27/11507 ,  G11C11/22 ,  H01L27/11504

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220199628A1

公开(公告)日：2022-06-23

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. SHARMA ,  Bernhard SELL ,  Chieh-Jen KU ,  Arnab SEN GUPTA ,  Matthew V. METZ ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG

IPC: H01L27/108 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US20220165735A1

公开(公告)日：2022-05-26

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US20230100860A1

公开(公告)日：2023-03-30

申请号：US17485306

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Christopher M. NEUMANN

IPC: H01L27/11507 ,  H01L27/108 ,  H01L25/065

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.

公开(公告)号：US20230097184A1

公开(公告)日：2023-03-30

申请号：US17485310

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sarah ATANASOV ,  Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L27/11507

Abstract: Embodiments of the present disclosure are directed to advanced integrated circuit structure fabrication and, in particular, integrated circuits with high dielectric constant (HiK) interfacial layering between an electrode and a ferroelectric (FE) or anti-ferroelectric (AFE) layer. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220199807A1

公开(公告)日：2022-06-23

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. Sharma ,  Bernhard SELL ,  Chieh-Jen KU ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG ,  Jason PECK ,  Tobias BROWN-HEFT

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：US20230111323A1

公开(公告)日：2023-04-13

申请号：US17485325

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Rahul RAMAMURTHY ,  Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Inanc MERIC ,  Uygar E. AVCI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/225

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230101111A1

公开(公告)日：2023-03-30

申请号：US17485317

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Shriram SHIVARAMAN ,  Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Jason PECK ,  Christopher M. NEUMANN

IPC: H01L27/11514 ,  H01L27/11507

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.