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    Three dimensional programmable logic circuit systems and methods
    1.
    发明授权
    Three dimensional programmable logic circuit systems and methods 有权

    公开(公告)号：US11489527B2

    公开(公告)日：2022-11-01

    申请号：US17354473

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Aravind Dasu ,  Ravi Gutala ,  Mahesh Iyer ,  Eriko Nurvitadhi ,  Archanna Srinivasan ,  Sean Atsatt ,  James Ball

    IPC: H03K19/17736 ,  H01L25/18 ,  H03K19/17768 ,  H03K19/1776

    Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY
    2.
    发明申请
    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY 有权

    公开(公告)号：US20210058086A1

    公开(公告)日：2021-02-25

    申请号：US16924044

    申请日：2020-07-08

    Applicant: Intel Corporation

    Inventor： Sean Atsatt

    IPC: H03K19/17736 ,  H01L25/18 ,  H03K19/1776 ,  H03K19/173 ,  H03K19/17756 ,  G11C15/00 ,  H03K19/17728

    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

    Coarse-grain programmable routing network for logic devices
    3.
    发明授权
    Coarse-grain programmable routing network for logic devices 有权

    公开(公告)号：US10587270B2

    公开(公告)日：2020-03-10

    申请号：US16439577

    申请日：2019-06-12

    Applicant: Intel Corporation

    Inventor： Gary Wallichs ,  Sean Atsatt

    IPC: H03K19/177 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17704

    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.

    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY
    4.
    发明申请
    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY 审中-公开

    公开(公告)号：US20190379380A1

    公开(公告)日：2019-12-12

    申请号：US16545381

    申请日：2019-08-20

    Applicant: Intel Corporation

    Inventor： Sean Atsatt

    IPC: H03K19/177 ,  H01L25/18 ,  G11C15/00 ,  H03K19/173

    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

    Stacked programmable integrated circuitry with smart memory
    7.
    发明授权
    Stacked programmable integrated circuitry with smart memory 有权

    公开(公告)号：US10749528B2

    公开(公告)日：2020-08-18

    申请号：US16545381

    申请日：2019-08-20

    Applicant: Intel Corporation

    Inventor： Sean Atsatt

    IPC: H03K19/17736 ,  H01L25/18 ,  H03K19/1776 ,  H03K19/173 ,  H03K19/17756 ,  G11C15/00 ,  H03K19/17728

    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY
    10.
    发明申请
    STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY 有权

    公开(公告)号：US20220231689A1

    公开(公告)日：2022-07-21

    申请号：US17713030

    申请日：2022-04-04

    Applicant: Intel Corporation

    Inventor： Sean Atsatt

    IPC: H03K19/17736 ,  H01L25/18 ,  H03K19/1776 ,  H03K19/173 ,  H03K19/17756 ,  G11C15/00 ,  H03K19/17728

    Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

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