公开(公告)号：US20220100514A1

公开(公告)日：2022-03-31

申请号：US17134367

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Anant NORI ,  Shankar BALACHANDRAN ,  Sreenivas SUBRAMONEY ,  Joydeep RAKSHIT ,  Vedvyas SHANBHOGUE ,  Avishaii ABUHATZERA ,  Belliappa KUTTANNA

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.

公开(公告)号：US20240143379A1

公开(公告)日：2024-05-02

申请号：US18466551

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Chandra PRAKASH ,  Aravinda PRASAD ,  Sreenivas SUBRAMONEY

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/45545 ,  G06F2009/45583

Abstract: It is provided an apparatus for enabling sequential prefetching inside a host, the apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to identify a first memory access pattern of an application in a guest virtual address space inside a virtual machine. The application is running inside the virtual machine and wherein the virtual machine is running on the host. The machine-readable instructions further comprise instructions to modify a layout of a guest physical address space, wherein the guest physical address space is corresponding to the guest virtual address space, to sequentialize a second memory access pattern in a host virtual address space. The second memory access pattern in the host virtual address space is corresponding to the first memory access pattern of the application in the guest virtual address space.

公开(公告)号：US20210089456A1

公开(公告)日：2021-03-25

申请号：US16729344

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Rahul BERA ,  Anant Vithal NORI ,  Sreenivas SUBRAMONEY

IPC: G06F12/0862

Abstract: Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.

公开(公告)号：US20190095331A1

公开(公告)日：2019-03-28

申请号：US15717939

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20220391128A1

公开(公告)日：2022-12-08

申请号：US17340866

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Saurabh JAIN ,  Srivatsa RANGACHAR SRINIVASA ,  Akshay Krishna RAMANATHAN ,  Gurpreet Singh KALSI ,  Kamlesh R. PILLAI ,  Sreenivas SUBRAMONEY

IPC: G06F3/06 ,  G06F7/523

Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

公开(公告)号：US20210019149A1

公开(公告)日：2021-01-21

申请号：US16729349

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： ADARSH CHAUHAN ,  Franck SALA ,  Jayesh GAUR ,  Zeev SPERBER ,  Lihu RAPPOPORT ,  Adi YOAZ ,  Sreenivas SUBRAMONEY

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.

公开(公告)号：US20250004772A1

公开(公告)日：2025-01-02

申请号：US18217499

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Kamlesh PILLAI ,  Vinodh GOPAL ,  Gurpreet Singh KALSI ,  Sreenivas SUBRAMONEY ,  Wajdi K. FEGHALI

IPC: G06F9/30

Abstract: Apparatus and method for a decompression hardware copy engine with efficient sequence overlapping copy. For example, one embodiment of an apparatus comprises: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor circuit to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor circuit to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine circuit to execute the copy instructions to produce the decompressed data stream.

公开(公告)号：US20220196798A1

公开(公告)日：2022-06-23

申请号：US17375017

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Chulong CHEN ,  Wenling Margaret HUANG ,  Saiveena KESARAJU ,  Ivan SIMÕES GASPAR ,  Pradyumna S. SINGH ,  Biji GEORGE ,  Dipan Kumar MANDAL ,  Om Ji OMER ,  Sreenivas SUBRAMONEY ,  Yuval AMIZUR ,  Leor BANIN ,  Hao CHEN ,  Nir DVORECKI ,  Shengbo XU

IPC: G01S7/41 ,  H01Q21/06 ,  G01S13/89 ,  G01S7/40 ,  G01S13/58

Abstract: According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.

公开(公告)号：US20210056030A1

公开(公告)日：2021-02-25

申请号：US17092093

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.