公开(公告)号：US20230092903A1

公开(公告)日：2023-03-23

申请号：US17480953

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas Pietambaram ,  Yosuke Kanaoka ,  Tchefor Ndukum

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: Methods and apparatus to embed host dies in a substrate are disclosed An apparatus includes a first die having a first side and a second side opposite the first side. The first side includes a first contact to be electrically coupled with a second die. The second side includes a second contact. The apparatus further includes a substrate including a metal layer and a dielectric material on the metal layer. The first die is encapsulated within the dielectric material. The second contact of the first die is bonded to the metal layer independent of an adhesive.

公开(公告)号：US20240079337A1

公开(公告)日：2024-03-07

申请号：US17929471

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tchefor Ndukum ,  Kristof Kuwawi Darmawikarta ,  Sheng Li ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

公开(公告)号：US20250112162A1

公开(公告)日：2025-04-03

申请号：US18375469

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Zheng Kang ,  Tchefor Ndukum ,  Yosuke Kanaoka ,  Jeremy Ecton ,  Gang Duan ,  Jefferson Kaplan ,  Yonggang Yong Li ,  Minglu Liu ,  Brandon C. Marin ,  Bai Nie ,  Srinivas Pietambaram ,  Shriya Seshadri ,  Bohan Shan ,  Deniz Turan ,  Vishal Bhimrao Zade

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.

公开(公告)号：US20250112124A1

公开(公告)日：2025-04-03

申请号：US18374555

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Leonel Arana ,  Gang Duan ,  Benjamin Duong ,  Hongxia Feng ,  Tarek Ibrahim ,  Brandon C. Marin ,  Tchefor Ndukum ,  Bai Nie ,  Srinivas Pietambaram ,  Bohan Shan ,  Matthew Tingey

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and below the IC die; and a gap within the dielectric material and extending around the metallization pattern.

公开(公告)号：US20230420378A1

公开(公告)日：2023-12-28

申请号：US17847407

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas V. Pietambaram ,  Kristof Kuwawi Darmawikarta ,  Tchefor Ndukum ,  Vejayakumaran Padavettan ,  Pooja Wadhwa ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/5381 ,  H01L21/4857 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.