公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US11640934B2

公开(公告)日：2023-05-02

申请号：US15941903

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Meizi Jiao ,  Chong Zhang ,  Hongxia Feng ,  Kevin Mccarthy

IPC: H01L23/498 ,  H01L23/00 ,  H05K1/11 ,  H01L21/48 ,  H05K3/06 ,  H05K3/40

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

公开(公告)号：US20230096835A1

公开(公告)日：2023-03-30

申请号：US17484519

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Bohan Shan ,  Hongxia Feng ,  Xiaoying Guo ,  Adam Schmitt ,  Jacob Vehonsky ,  Steve Cho ,  Leonel Arana

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

公开(公告)号：US20230095281A1

公开(公告)日：2023-03-30

申请号：US17484499

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Hongxia Feng ,  Xiaoying Guo ,  Steve Cho ,  Jung Kyu Han ,  Changhua Liu ,  Leonel Arana ,  Rahul Manepalli ,  Dingying Xu ,  Amram Eitan

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/488 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.

公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US20240222210A1

公开(公告)日：2024-07-04

申请号：US18091548

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.

公开(公告)号：US20240213170A1

公开(公告)日：2024-06-27

申请号：US18086293

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.