公开(公告)号：US20220237850A1

公开(公告)日：2022-07-28

申请号：US17669126

申请日：2022-02-10

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC分类号： G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220076118A1

公开(公告)日：2022-03-10

申请号：US17404153

申请日：2021-08-17

申请人： Intel Corporation

发明人： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC分类号： G06N3/08 ,  G06N20/10 ,  G06N20/00

摘要： In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11210265B2

公开(公告)日：2021-12-28

申请号：US16869223

申请日：2020-05-07

申请人： Intel Corporation

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F16/13 ,  G06F16/11 ,  G06F16/172 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/0831

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US11182948B2

公开(公告)日：2021-11-23

申请号：US17127740

申请日：2020-12-18

申请人： Intel Corporation

发明人： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC分类号： G06T15/00 ,  G06T15/30 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60

摘要： Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20190355091A1

公开(公告)日：2019-11-21

申请号：US15982680

申请日：2018-05-17

申请人： Intel Corporation

发明人： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC分类号： G06T3/40 ,  G06T1/20

摘要： Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.

公开(公告)号：US10152822B2

公开(公告)日：2018-12-11

申请号：US15477019

申请日：2017-04-01

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC分类号： G06T15/08 ,  H04N5/369 ,  G02B27/01 ,  G06T15/10 ,  G06T15/60 ,  G06K9/00 ,  H04N5/232

摘要： An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20180314931A1

公开(公告)日：2018-11-01

申请号：US15499896

申请日：2017-04-28

申请人： Intel Corporation

发明人： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC分类号： G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC分类号： G06T1/20 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/00

摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170337728A1

公开(公告)日：2017-11-23

申请号：US15156809

申请日：2016-05-17

申请人： Intel Corporation

发明人： Tomer Bar-On

IPC分类号： G06T15/20 ,  G06T15/30 ,  G06T11/40 ,  G06T17/20 ,  G06T1/20

CPC分类号： G06T15/20 ,  G06T1/20 ,  G06T7/50 ,  G06T11/40 ,  G06T15/005 ,  G06T15/30 ,  G06T17/20

摘要： A mechanism for efficient triangle rendering is described. A method of embodiments, as described herein, includes detecting a plurality of triangles during rendering of a digital image, computing an error bound as a function of depth value gradients and determining whether one or more of the plurality of triangles relative to a projection screen based on the error bound computation.

公开(公告)号：US20240177395A1

公开(公告)日：2024-05-30

申请号：US18324611

申请日：2023-05-26

申请人： Intel Corporation

发明人： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC分类号： G06T15/00 ,  G06T15/30 ,  G06T15/40

CPC分类号： G06T15/005 ,  G06T15/30 ,  G06T15/40

摘要： Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20240004833A1

公开(公告)日：2024-01-04

申请号：US18349386

申请日：2023-07-10

申请人： Intel Corporation

发明人： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC分类号： G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

CPC分类号： G06F16/13 ,  G06F9/3836 ,  G06F9/30 ,  G06F9/38 ,  G06F16/113 ,  G06F16/172 ,  G06F9/461 ,  G06F2201/84 ,  G06F12/1036

摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.