公开(公告)号：US20230300063A1

公开(公告)日：2023-09-21

申请号：US18200342

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Helia A. NAEIMI ,  Amedeo SAPIO ,  John Andrew FINGERHUT ,  Yi LI ,  Yanfang LE

IPC: H04L45/16 ,  H04L69/22

CPC classification number: H04L45/16 ,  H04L69/22

Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.

公开(公告)号：US20210320866A1

公开(公告)日：2021-10-14

申请号：US17359244

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Yanfang LE ,  Junggun LEE ,  Jeremias BLENDIN ,  Grzegorz JERECZEK ,  Georgios NIKOLAIDIS

IPC: H04L12/801 ,  H04L12/931 ,  H04L12/851 ,  H04L12/861

Abstract: Examples described herein relate to a switch that is to receive a message identifying congestion in a second switch; drop the message; generate a pause frame; and cause transmission of the pause frame to at least one sender of packets to a congested queue in the second switch. In some examples, the message includes one or more of: a destination IP address, Differentiated Services Code Point (DSCP) value, or pause duration for the congested queue. In some examples, the DSCP value is to identify a traffic class of the congested queue. In some examples, the pause frame is consistent with Priority Flow Control (PFC) of IEEE 802.1Qbb (2011). In some examples, the switch is to: store, from the message identifying congestion in the second switch, congestion information associated with the congested queue comprising one or more of: destination internet protocol (IP) address, Differentiated Services Code Point (DSCP) value, or pause end time of the congested queue.

公开(公告)号：US20230239196A1

公开(公告)日：2023-07-27

申请号：US18130383

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Junggun LEE ,  Anurag AGRAWAL ,  Yi LI ,  Jeremias BLENDIN ,  Yanfang LE

IPC: H04L41/0681 ,  H04L69/22 ,  H04L47/11

CPC classification number: H04L41/0681 ,  H04L47/115 ,  H04L69/22

Abstract: An apparatus is described. The apparatus includes electronic circuitry to support multiple flows within a network. The electronic circuitry to determine respective telemetry information for the multiple flows and inject an alarm message into a particular one of the multiple flows upon an alarm condition being reached for the particular one flow. The alarm message includes a multi-bit error code that describes the alarm condition. The multi-bit error code is one of multiple, possible multi-bit error codes.

公开(公告)号：US20220060418A1

公开(公告)日：2022-02-24

申请号：US17515222

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Yanfang LE ,  Daniel A. ALVAREZ ,  Amedeo SAPIO ,  John Andrew FINGERHUT

IPC: H04L12/741 ,  H04L12/721

Abstract: Examples described herein relate to a switch comprising: circuitry, when operational, to receive a packet comprising a header and a payload and in conjunction with performance of computation on the packet payload, forward the packet header, but not the payload, to a destination endpoint. In some examples, the destination endpoint of the packet is to perform management of reliable transport. In some examples, the circuitry includes programmable data plane circuitry comprising ingress pipeline or egress pipeline and one or more match action units (MAUs) to perform processing of the payload, wherein the programmable data plane circuitry is to perform computation on the packet payload.

公开(公告)号：US20230038307A1

公开(公告)日：2023-02-09

申请号：US17879410

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Jeremias BLENDIN ,  Junggun LEE ,  Yanfang LE

IPC: H04L45/00 ,  H04L45/28 ,  H04L47/125

Abstract: Examples described herein relate to a network interface device comprising: circuitry, when operational, to: in response to congestion related to a link, cause transmission of link event information to at least one sender of packets to the link, wherein the link event information is to identify congestion information of at least one link other than the link.

公开(公告)号：US20220124035A1

公开(公告)日：2022-04-21

申请号：US17561839

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Junggun LEE ,  Jeremias BLENDIN ,  Yanfang LE ,  Rong PAN ,  Mark DEBBAGE ,  Robert SOUTHWORTH

IPC: H04L47/12 ,  H04L47/2483 ,  H04L43/0817 ,  H04L43/0882 ,  H04L43/0888

Abstract: Examples described herein relate to a switch circuitry that includes circuitry to determine if a received packet comprises a control packet; circuitry to determine congestion metrics based on receipt of at least one control packet, wherein the at least one control packet comprises a Request To Send (RTS) or Clear To Send (CTS); and circuitry to transmit at least one of the congestion metrics in at least one packet to a sender and/or receiver network interface device.