NETWORK INTERFACE DEVICE-BASED COMPUTATIONS
    1.
    发明公开

    公开(公告)号:US20230300063A1

    公开(公告)日:2023-09-21

    申请号:US18200342

    申请日:2023-05-22

    CPC classification number: H04L45/16 H04L69/22

    Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.

    FLOW CONTROL TECHNOLOGIES
    2.
    发明申请

    公开(公告)号:US20210320866A1

    公开(公告)日:2021-10-14

    申请号:US17359244

    申请日:2021-06-25

    Abstract: Examples described herein relate to a switch that is to receive a message identifying congestion in a second switch; drop the message; generate a pause frame; and cause transmission of the pause frame to at least one sender of packets to a congested queue in the second switch. In some examples, the message includes one or more of: a destination IP address, Differentiated Services Code Point (DSCP) value, or pause duration for the congested queue. In some examples, the DSCP value is to identify a traffic class of the congested queue. In some examples, the pause frame is consistent with Priority Flow Control (PFC) of IEEE 802.1Qbb (2011). In some examples, the switch is to: store, from the message identifying congestion in the second switch, congestion information associated with the congested queue comprising one or more of: destination internet protocol (IP) address, Differentiated Services Code Point (DSCP) value, or pause end time of the congested queue.

    NETWORK INTERFACE DEVICE-BASED COMPUTATIONS

    公开(公告)号:US20220060418A1

    公开(公告)日:2022-02-24

    申请号:US17515222

    申请日:2021-10-29

    Abstract: Examples described herein relate to a switch comprising: circuitry, when operational, to receive a packet comprising a header and a payload and in conjunction with performance of computation on the packet payload, forward the packet header, but not the payload, to a destination endpoint. In some examples, the destination endpoint of the packet is to perform management of reliable transport. In some examples, the circuitry includes programmable data plane circuitry comprising ingress pipeline or egress pipeline and one or more match action units (MAUs) to perform processing of the payload, wherein the programmable data plane circuitry is to perform computation on the packet payload.

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