公开(公告)号：US11562940B2

公开(公告)日：2023-01-24

申请号：US16296898

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： Elizabeth Nofen ,  James C. Matayabas, Jr. ,  Yawei Liang ,  Yiqun Bai

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/367 ,  F28F21/08 ,  H01L21/48

Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200286806A1

公开(公告)日：2020-09-10

申请号：US16296898

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： Elizabeth Nofen ,  James C. Matayabas, JR. ,  Yawei Liang ,  Yiqun Bai

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  F28F21/08

Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US11804470B2

公开(公告)日：2023-10-31

申请号：US16548255

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Kaizad Mistry ,  Paul R. Start ,  Nisha Ananthakrishnan ,  Yawei Liang ,  Jigneshkumar P. Patel ,  Sairam Agraharam ,  Liwei Wang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/73253

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.