公开(公告)号：US07476924B2

公开(公告)日：2009-01-13

申请号：US11550553

申请日：2006-10-18

申请人： Je-Min Park ,  Ho-Jin Oh

发明人： Je-Min Park ,  Ho-Jin Oh

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76889

摘要： A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

摘要翻译： 具有凹入的着陆焊盘的半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 第一着陆焊盘通过下层间介质层设置成与半导体衬底接触。 第二着陆焊盘通过下层间介质层设置成也与半导体衬底接触。 金属硅化物层设置在第二着陆焊盘上。 金属硅化物层设置成比第一着陆焊盘的顶表面低。 中间层间介电层设置在下层间介质层上。 导电线设置在中间层间电介质层上。 接触插头设置在导电线和金属硅化物层之间。 金属硅化物层和接触插塞之间的设计的接触区域被保护以防止无意的蚀刻。

公开(公告)号：US07745899B2

公开(公告)日：2010-06-29

申请号：US11832270

申请日：2007-08-01

申请人： Ho-Jin Oh ,  Je-Min Park ,  Jee-Eun Jung

发明人： Ho-Jin Oh ,  Je-Min Park ,  Jee-Eun Jung

IPC分类号： H01L29/423 ,  H01L21/3205

CPC分类号： G03F1/70 ,  G03F1/00 ,  H01L29/4238

摘要： An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.

摘要翻译： 公开了用于形成栅极线的光掩模的实施例和使用光掩模制造半导体器件的方法。 光掩模包括光掩模基板，限定栅极线的栅极线掩模图案，栅极线与半导体衬底上的至少一个有源区交叉并且平行布置，形成在每个栅极线掩模图案的两侧上的栅极掩模图案，以及 在相邻的闸板掩模图案之间形成的接头，并且包括分离区域。 可以使用光掩模形成相对较大的栅极贴片掩模图案。 并且通过大的栅极片掩模图案可以改善有源区边界的短沟道效应，从而可以提高半导体器件的特性和可靠性。

公开(公告)号：US20070152257A1

公开(公告)日：2007-07-05

申请号：US11550553

申请日：2006-10-18

申请人： Je-Min Park ,  Ho-Jin Oh

发明人： Je-Min Park ,  Ho-Jin Oh

IPC分类号： H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76889

摘要： A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

摘要翻译： 具有凹入的着陆焊盘的半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。 第一着陆焊盘通过下层间介质层设置成与半导体衬底接触。 第二着陆焊盘通过下层间介质层设置成也与半导体衬底接触。 金属硅化物层设置在第二着陆焊盘上。 金属硅化物层设置成比第一着陆焊盘的顶表面低。 中间层间介电层设置在下层间介质层上。 导电线设置在中间层间电介质层上。 接触插头设置在导电线和金属硅化物层之间。 金属硅化物层和接触插塞之间的设计的接触区域被保护以防止无意的蚀刻。

公开(公告)号：US20160027787A1

公开(公告)日：2016-01-28

申请号：US14847324

申请日：2015-09-08

申请人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

发明人： Je-Min Park ,  Seok-Hyun Lim ,  Tae-Yong Song ,  Hyun-Chul Yoon ,  Yoo-Sang Hwang ,  Hyeon-Ok Jung

IPC分类号： H01L27/108 ,  H01L21/3213

CPC分类号： H01L27/10855 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

摘要翻译： 电子器件可以包括衬底和衬底上的多个间隔开的衬垫。 每个垫可以包括第一，第二，第三和第四侧，第一和第三侧可以是基本上直的相对侧，并且第二和第四侧可以是相对的弯曲的侧面。 还讨论了相关方法，设备和结构。

公开(公告)号：US20120217631A1

公开(公告)日：2012-08-30

申请号：US13469434

申请日：2012-05-11

申请人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

发明人： Dae-Ik Kim ,  Je-Min Park ,  Chang-Suk Hyun

IPC分类号： H01L23/52

CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.

摘要翻译： 集成电路器件包括沿着第一方向在衬底上彼此间隔开的第一和第二导电结构。 第一和第二导电结构在基本上垂直于第一方向的第二方向上延伸。 接触塞被插入在第一和第二导电结构之间，并且通过接触插塞的相对侧上的相应气​​隙沿第一方向与其分离。 气隙限定分别使接触塞与第一和第二导电结构电绝缘的第一和第二空气间隔件。 上绝缘层覆盖第一和第二空气间隔件以及第一和第二导电结构。 空气间隔件可以充分降低导电结构之间的负载电容。 还讨论了相关的制造方法。

公开(公告)号：US07601630B2

公开(公告)日：2009-10-13

申请号：US11020827

申请日：2004-12-22

申请人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Dong-Won Shin ,  Yoo-Sang Hwang

IPC分类号： H01L21/4763 ,  H01L21/8239 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

摘要： A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

摘要翻译： 制造半导体存储器件的方法和形成电阻器和蚀刻保护层的结构以降低接触电阻。 根据本发明的制造半导体存储器件的方法包括在具有单元阵列区域，芯区域和周边区域的半导体衬底上形成绝缘层，每个晶体管阵列区域和外围区域都具有形成在其中的至少一个晶体管，并且形成第一 在绝缘层上的芯区域中的着陆焊盘和外围区域中的第二着陆焊盘，第一着陆焊盘与第一导电线的一部分重叠。 本发明通过简化的过程降低了接触电阻并且防止或最小化由不对准引起的设备故障。

公开(公告)号：US07575971B2

公开(公告)日：2009-08-18

申请号：US11464134

申请日：2006-08-11

申请人： Je-Min Park ,  Jin-Jun Park

发明人： Je-Min Park ,  Jin-Jun Park

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852

摘要： According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

摘要翻译： 根据一些实施例，电容器包括存储导电图案，存储电极，其具有包围存储导电图案的互补构件，以补充存储电极的蚀刻损耗，设置在存储电极上的电介质层和平板电极 设置在电介质层上。 由于互补部件在几个蚀刻工艺期间补偿存储电极的蚀刻损耗，因此可以防止存储电极的结构稳定性的劣化。 此外，由于互补部件形成在存储电极的上部，所以存储电极可以具有足够的厚度以增强包括存储电极的电容器的电特性。

公开(公告)号：US07446043B2

公开(公告)日：2008-11-04

申请号：US11416328

申请日：2006-05-02

申请人： Je-Min Park ,  Byung-Yoon Kim

发明人： Je-Min Park ,  Byung-Yoon Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/3011

摘要： A contact structure having silicide layers, a semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device are provided. The contact structure includes a first conductive region and a second conductive region on a substrate. An insulating layer covers the first and second conductive regions. A first contact hole and a second contact hole are formed through the insulating layer and expose the first and second conductive regions, respectively. A first silicide layer having a first thickness is on the first conductive region exposed by the first contact hole. A second silicide layer having a second thickness different than the first thickness is on the second conductive region exposed by the second contact hole.

摘要翻译： 提供具有硅化物层的接触结构，采用该硅化物层的半导体器件以及制造接触结构和半导体器件的方法。 接触结构包括第一导电区域和衬底上的第二导电区域。 绝缘层覆盖第一和第二导电区域。 通过绝缘层形成第一接触孔和第二接触孔，分别露出第一和第二导电区域。 具有第一厚度的第一硅化物层在由第一接触孔暴露的第一导电区上。 具有不同于第一厚度的第二厚度的第二硅化物层在由第二接触孔暴露的第二导电区域上。

公开(公告)号：US20070259494A1

公开(公告)日：2007-11-08

申请号：US11780026

申请日：2007-07-19

申请人： Je-Min Park ,  Yoo-Sang Hwang

发明人： Je-Min Park ,  Yoo-Sang Hwang

IPC分类号： H01L21/8234 ,  H01L21/4763

CPC分类号： H01L28/20 ,  H01L21/76838 ,  H01L27/0629

摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

摘要翻译： 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US20070059931A1

公开(公告)日：2007-03-15

申请号：US11416328

申请日：2006-05-02

申请人： Je-Min Park ,  Byung-Yoon Kim

发明人： Je-Min Park ,  Byung-Yoon Kim

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/3011

摘要： A contact structure having silicide layers, a semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device are provided. The contact structure includes a first conductive region and a second conductive region on a substrate. An insulating layer covers the first and second conductive regions. A first contact hole and a second contact hole are formed through the insulating layer and expose the first and second conductive regions, respectively. A first silicide layer having a first thickness is on the first conductive region exposed by the first contact hole. A second silicide layer having a second thickness different than the first thickness is on the second conductive region exposed by the second contact hole.

摘要翻译： 提供具有硅化物层的接触结构，采用该硅化物层的半导体器件以及制造接触结构和半导体器件的方法。 接触结构包括第一导电区域和衬底上的第二导电区域。 绝缘层覆盖第一和第二导电区域。 通过绝缘层形成第一接触孔和第二接触孔，分别露出第一和第二导电区域。 具有第一厚度的第一硅化物层在由第一接触孔暴露的第一导电区上。 具有不同于第一厚度的第二厚度的第二硅化物层在由第二接触孔暴露的第二导电区域上。