公开(公告)号：US5175822A

公开(公告)日：1992-12-29

申请号：US368679

申请日：1989-06-19

申请人： Jerry D. Dixon ,  Don S. Keener ,  Howard J. Locker ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Neal A. Osborn

发明人： Jerry D. Dixon ,  Don S. Keener ,  Howard J. Locker ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Neal A. Osborn

IPC分类号： G06F13/14 ,  G06F12/06

CPC分类号： G06F12/0676

摘要： Apparatus for assigning addresses to devices connected to a small computer system interface (SCSI) bus. A second configure bus interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：US4489378A

公开(公告)日：1984-12-18

申请号：US270750

申请日：1981-06-05

申请人： Jerry D. Dixon ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Gerald U. Merckel

发明人： Jerry D. Dixon ,  Gerald A. Marazas ,  Andrew B. McNeill ,  Gerald U. Merckel

IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F9/06 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F13/122 ,  G06F12/0866 ,  G06F2212/502

摘要： When transferring data to a cache memory from an attachment data storage device, additional unrequested information can be transferred at the same time if it is likely that this additional data will soon be requested. The average quantity of data transferred to the cache memory in each operation can be automatically and continually varied in order to maximize the performance advantage provided by the cache memory. When a record of data is requested by the host processor, data is transferred to the cache memory from an attachment data storage device in increments of fixed-length data blocks each containing a sequence of data records, with the number of transferred blocks being determined by the position of a requested data record in its respective data block, and the average number of blocks transferred in any one operation being varied by adjusting threshold position values at which second or third data blocks are transferred.

摘要翻译： 当从附件数据存储设备传送数据到高速缓冲存储器时，如果很可能要求这个附加数据，则可以同时传送额外的未请求的信息。 在每个操作中传输到高速缓冲存储器的数据的平均数量可以被自动地和连续地变化，以便最大化缓存存储器提供的性能优势。 当主处理器请求数据记录时，数据以固定长度的数据块的增量从附件数据存储设备传送到高速缓冲存储器，每个固定长度数据块包含一系列数据记录，传送块的数量由 通过调整传送第二或第三数据块的阈值位置值来改变在其各自的数据块中所请求的数据记录的位置以及在任何一个操作中传送的块的平均数量。

公开(公告)号：US5550990A

公开(公告)日：1996-08-27

申请号：US400425

申请日：1995-03-03

申请人： Don S. Keener ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Kevin L. Scheiern ,  Richard W. Voorhees ,  Edward I. Wachtel

发明人： Don S. Keener ,  Andrew B. McNeill ,  Thomas H. Newsom ,  Kevin L. Scheiern ,  Richard W. Voorhees ,  Edward I. Wachtel

IPC分类号： G06F13/36 ,  G06F13/40

CPC分类号： G06F13/4027

摘要： Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

摘要翻译： 用于将具有良好定义的体系结构的总线物理划分为物理实体的布置，其中分区在逻辑上对于计算机和通过总线通信的设备是透明的，并且用于避免由于架构允许的动作的范围而潜在地产生的问题。 现有安排具有相关性的典型总线架构是与SCSI（小型计算机系统接口）总线相关联的。 允许在架构上发生的潜在问题涉及：（a）数据安全/完整性的暴露; （b）由于使用信号速率引起的过多的信号衰减，尽管架构允许这种信号速率对于架构也允许的特定总线负载环境是不合适的; （c）防止计算机与多个存储设备之间的数据并行传输的限制; （d）限制不适当地限制可连接到一条逻辑总线路径（计算机的一个输入 - 输出通道）的设备数量。 所公开的布置将总线划分成两个或更多个物理实体，其将计算机显示为一个逻辑实体。

公开(公告)号：US5119498A

公开(公告)日：1992-06-02

申请号：US365269

申请日：1989-06-12

申请人： Andrew B. McNeill ,  Thomas H. Newsom ,  Neal A. Osborn ,  Eddie M. Reid

发明人： Andrew B. McNeill ,  Thomas H. Newsom ,  Neal A. Osborn ,  Eddie M. Reid

IPC分类号： G06F3/00 ,  G06F13/40 ,  G06F15/00 ,  H01R9/00 ,  H01R29/00

CPC分类号： G06F13/4063 ,  G06F13/409 ,  Y10S439/955

摘要： A plug-in feature board for a computer system has special circuitry to permit the board to customize itself to the particular slot into which it is inserted. Computers of the type intended for individual use or use in small networks typically provide insertion slots including connectors to permit feature boards to be added and connected to a bus of the computer for adding new function or capacity. As the computing power of such systems has increased there have been increases in the size of portions of the connecting bus to permit improvements in data transfer performance. In a given computer system there are often two or more bus connector configurations presented in respective slots. By so converting electrical states at selected connector positions as to provide signal information for determining bus configuration for the slot, special logic provided on the board is enabled to determine the characteristics of the slot in which the board is placed and customizes the board to respond or limit response in accordance with the requirements for that configuration. By so adapting to the slot the board achieves enhanced applicability and avoids certain system disabling malfunctions which can occur when a board is plugged into a slot for which it is not configured.

公开(公告)号：US5033049A

公开(公告)日：1991-07-16

申请号：US364363

申请日：1989-06-12

申请人： Don S. Keener ,  Andrew B. McNeill ,  Kevin L. Scheiern

发明人： Don S. Keener ,  Andrew B. McNeill ,  Kevin L. Scheiern

IPC分类号： G06F11/22 ,  G06F11/26 ,  G06F11/267 ,  G06F13/00

CPC分类号： G06F11/2221 ,  G06F11/261 ,  G06F11/221

摘要： On board diagnostic capability for a SCSI controller is provided within an adapter by providing a gate array driven by a microprocessor on board the adapter. The gate array has data and control inputs driven from the microprocessor and data and control outputs which are dot OR'ed with corresponding in/out terminals of the SCSI controller. A reset signal from a SCSI bus forms a further input to the gate array. For testing purposes the microprocessor drives the gate array inputs to simulate a fault-free or faulty device. The microprocessor detects the response of the SCSI controller to the device simulation and thereby can determine the state of health of the SCSI controller.

公开(公告)号：US5204951A

公开(公告)日：1993-04-20

申请号：US416210

申请日：1989-10-02

申请人： Don S. Keener ,  Andrew B. McNeill ,  Edward I. Wachtel

发明人： Don S. Keener ,  Andrew B. McNeill ,  Edward I. Wachtel

IPC分类号： G06F13/362 ,  G06F13/22 ,  G06F13/24

CPC分类号： G06F13/225

摘要： Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

公开(公告)号：US07543178B2

公开(公告)日：2009-06-02

申请号：US12057403

申请日：2008-03-28

申请人： Andrew B. McNeill ,  Thomas H. Newsom

发明人： Andrew B. McNeill ,  Thomas H. Newsom

IPC分类号： G06F11/00

CPC分类号： G06F11/008

摘要： A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.

摘要翻译： 存储子系统，例如磁盘驱动器阵列，管理存储子系统中的磁盘驱动器的方法及其程序产品。 存储子系统可以是独立磁盘（RAID）的冗余阵列，并且各个磁盘驱动器可以是具有自监控，分析和报告技术（SMART）功能的驱动器。 当其中一个驱动器显示即将发生的故障时，故障磁盘的磁盘映像将构建在可用的备用磁盘上。 图像完成后，可能会更换故障磁盘，无需停机时间重建故障磁盘。

公开(公告)号：US5022077A

公开(公告)日：1991-06-04

申请号：US398820

申请日：1989-08-25

申请人： Richard Bealkowski ,  John W. Blackledge, Jr. ,  Doyle S. Cronk ,  Richard A. Dayan ,  Jerry D. Dixon ,  Scott G. Kinnear ,  George D. Kovach ,  Andrew B. McNeill ,  Matthew S. Palka, Jr. ,  Robert Sachsenmaier ,  Edward I. Wachtel ,  Kevin M. Zyvoloski

发明人： Richard Bealkowski ,  John W. Blackledge, Jr. ,  Doyle S. Cronk ,  Richard A. Dayan ,  Jerry D. Dixon ,  Scott G. Kinnear ,  George D. Kovach ,  Andrew B. McNeill ,  Matthew S. Palka, Jr. ,  Robert Sachsenmaier ,  Edward I. Wachtel ,  Kevin M. Zyvoloski

IPC分类号： G06F13/10 ,  G06F9/445 ,  G06F12/14 ,  G06F21/22

CPC分类号： G06F9/4406

摘要： An apparatus and method for protecting BIOS stored on a direct access storage device into a personnal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, a protection means and at least one direct access storage device. The read only memory includes a first portion of BIOS and data representing the type of system processor and system planar I/O configuration. The first portion of BIOS initializes the system and the direct access storage device, and resets the protection means in order to read in a master boot record into the random access memory from a protectable partition on the direct access storage device.

公开(公告)号：US20080178038A1

公开(公告)日：2008-07-24

申请号：US12057403

申请日：2008-03-28

申请人： Andrew B. McNeill ,  Thomas H. Newsom

发明人： Andrew B. McNeill ,  Thomas H. Newsom

IPC分类号： G06F11/20

CPC分类号： G06F11/008

摘要： A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.

摘要翻译： 存储子系统，例如磁盘驱动器阵列，管理存储子系统中的磁盘驱动器的方法及其程序产品。 存储子系统可以是独立磁盘（RAID）的冗余阵列，并且各个磁盘驱动器可以是具有自监控，分析和报告技术（SMART）功能的驱动器。 当其中一个驱动器显示即将发生的故障时，故障磁盘的磁盘映像将构建在可用的备用磁盘上。 图像完成后，可能会更换故障磁盘，无需停机时间重建故障磁盘。

公开(公告)号：US5170471A

公开(公告)日：1992-12-08

申请号：US818654

申请日：1992-01-06

申请人： Francis M. Bonevento ,  Douglas R. Chrisholm ,  Sammy D. Dodds ,  Dhruvkumar M. Desai ,  Ernest N. Mandese ,  Andrew B. McNeill ,  Richard N. Mendelson

发明人： Francis M. Bonevento ,  Douglas R. Chrisholm ,  Sammy D. Dodds ,  Dhruvkumar M. Desai ,  Ernest N. Mandese ,  Andrew B. McNeill ,  Richard N. Mendelson

IPC分类号： G06F13/12

CPC分类号： G06F13/126

摘要： A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

摘要翻译： 命令接口包括用于在主机处理器和至少一个可能具有连接设备的智能子系统之间传送信息的端口。 命令接口端口接收来自主处理器的直接命令或间接命令，哪些命令指示要由一个子系统或连接的设备执行的操作的类型。 注意端口接收来自主处理器的代码，其指示在命令接口端口处接收到直接命令或间接命令中的哪一个，并且还指示一个智能子系统或设备将执行哪一个 命令。 命令忙/状态端口从一个智能子系统接收指示命令接口端口和注意端口是否忙碌的代码，以及一个智能子系统是否接受或拒绝命令。 主机处理器可以读取此端口，而无需更改或更新代码。