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公开(公告)号：US12125545B2
公开(公告)日：2024-10-22
申请号：US17689182
申请日：2022-03-08
Applicant: Kioxia Corporation
Inventor： Reiko Sumi , Takashi Maeda , Hidehiro Shiga
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/08
Abstract: A semiconductor memory device includes a driver that, in a write operation, applies a first voltage to a first select gate line, applies a second voltage lower than the first voltage to a second select gate line, applies a third voltage equal to or higher than the first voltage to a first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to a second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to a first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to a second dummy word line on a lowermost layer.
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公开(公告)号：US11715534B2
公开(公告)日：2023-08-01
申请号：US17459441
申请日：2021-08-27
Applicant: KIOXIA CORPORATION
Inventor： Rieko Funatsuki , Takashi Maeda , Reiko Sumi , Reika Tanaka , Masumi Saitoh
CPC classification number: G11C16/3445 , G11C16/0433 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3404
Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.
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公开(公告)号：US12165708B2
公开(公告)日：2024-12-10
申请号：US18068605
申请日：2022-12-20
Applicant: KIOXIA CORPORATION
Inventor： Reiko Sumi , Kazutaka Ikegami
Abstract: A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.
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公开(公告)号：US12211567B2
公开(公告)日：2025-01-28
申请号：US17816836
申请日：2022-08-02
Applicant: Kioxia Corporation
Inventor： Kazutaka Ikegami , Takashi Maeda , Reiko Sumi
Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.
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