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公开(公告)号:US10540759B2
公开(公告)日:2020-01-21
申请号:US15627834
申请日:2017-06-20
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Thomas Krah , Shifang Li , Heiko Eisenbach , Moritz Stoerring
IPC: G06K9/00 , G06T7/00 , G06T7/73 , H01L21/66 , G06T7/13 , G01B11/00 , G01B11/24 , G06T7/60 , H01L21/306
Abstract: Wafer edge profile images are analyzed at locations around a bonded wafer, which may have a top wafer and a carrier wafer. An offset curve is generated based on the wafer edge profile images. Displacement of the top wafer to the carrier wafer is determined based on the offset curve. The wafer edge profile images may be generated at multiple locations around the wafer. The wafer edge profile images may be shadowgram images. A system to determine displacement of the top wafer to the carrier wafer can include an imaging system connected with a controller.
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公开(公告)号:US20190067060A1
公开(公告)日:2019-02-28
申请号:US16113930
申请日:2018-08-27
Applicant: KLA-Tencor Corporation
Inventor: Martin Plihal , Brian Duffy , Mike VonDenHoff , Andrew Cross , Kaushik Sah , Antonio Mani
Abstract: Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.
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公开(公告)号:US20180321168A1
公开(公告)日:2018-11-08
申请号:US15671230
申请日:2017-08-08
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Andrew James Cross , Antonio Mani
IPC: G01N23/225
Abstract: Information from metrology tools can be used during inspection or review with a scanning electron microscope. Metrology measurements of a wafer are interpolated and/or extrapolated over a field, which creates modified metrology data. The modified metrology data is associated with defect attributes from inspection measurements of a wafer. A wafer review sampling plan is generated based on the defect attributes and the modified metrology data. The wafer review sampling plan can be used during review of a wafer using the scanning electron microscope.
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公开(公告)号:US10068323B2
公开(公告)日:2018-09-04
申请号:US15290990
申请日:2016-10-11
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Andrew James Cross
IPC: G06T7/00 , H01L21/66 , H01L21/033
Abstract: A design aware system, method, and computer program product are provided for detecting overlay-related defects in multi-patterned fabricated devices. In use, a design of a multi-patterned fabricated device is received by a computer system. Then, the computer system automatically determines from the design one or more areas of the design that are prone to causing overlay errors. Further, an indication of the determined one or more areas is output by the computer system to an inspection system for use in inspecting a multi-patterned device fabricated in accordance with the design.
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公开(公告)号:US20180150952A1
公开(公告)日:2018-05-31
申请号:US15627834
申请日:2017-06-20
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Thomas Krah , Shifang Li , Heiko Eisenbach , Moritz Stoerring
Abstract: Wafer edge profile images are analyzed at locations around a bonded wafer, which may have a top wafer and a carrier wafer. An offset curve is generated based on the wafer edge profile images. Displacement of the top wafer to the carrier wafer is determined based on the offset curve. The wafer edge profile images may be generated at multiple locations around the wafer. The wafer edge profile images may be shadowgram images. A system to determine displacement of the top wafer to the carrier wafer can include an imaging system connected with a controller.
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公开(公告)号:US10818001B2
公开(公告)日:2020-10-27
申请号:US16241467
申请日:2019-01-07
Applicant: KLA-TENCOR CORPORATION
Inventor: Wing-Shan Ribi Leung , Kaushik Sah , Allen Park , Andrew Cross
Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.
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公开(公告)号:US10699926B2
公开(公告)日:2020-06-30
申请号:US16113930
申请日:2018-08-27
Applicant: KLA-Tencor Corporation
Inventor: Martin Plihal , Brian Duffy , Mike VonDenHoff , Andrew Cross , Kaushik Sah , Antonio Mani
Abstract: Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.
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公开(公告)号:US10598617B2
公开(公告)日:2020-03-24
申请号:US15671230
申请日:2017-08-08
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Andrew James Cross , Antonio Mani
IPC: G06K9/00 , G01N23/2251 , H01L21/66 , G01N21/956 , G01N21/88 , G01N21/95
Abstract: Information from metrology tools can be used during inspection or review with a scanning electron microscope. Metrology measurements of a wafer are interpolated and/or extrapolated over a field, which creates modified metrology data. The modified metrology data is associated with defect attributes from inspection measurements of a wafer. A wafer review sampling plan is generated based on the defect attributes and the modified metrology data. The wafer review sampling plan can be used during review of a wafer using the scanning electron microscope.
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公开(公告)号:US20200082523A1
公开(公告)日:2020-03-12
申请号:US16241467
申请日:2019-01-07
Applicant: KLA-TENCOR CORPORATION
Inventor: Wing-Shan Ribi Leung , Kaushik Sah , Allen Park , Andrew Cross
Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.
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10.
公开(公告)号:US20170294012A1
公开(公告)日:2017-10-12
申请号:US15290990
申请日:2016-10-11
Applicant: KLA-Tencor Corporation
Inventor: Kaushik Sah , Andrew James Cross
CPC classification number: G06T7/0004 , G06T2207/30148 , H01L21/0332 , H01L21/0338 , H01L22/12 , H01L22/20
Abstract: A design aware system, method, and computer program product are provided for detecting overlay-related defects in multi-patterned fabricated devices. In use, a design of a multi-patterned fabricated device is received by a computer system. Then, the computer system automatically determines from the design one or more areas of the design that are prone to causing overlay errors. Further, an indication of the determined one or more areas is output by the computer system to an inspection system for use in inspecting a multi-patterned device fabricated in accordance with the design.
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