Identifying Nuisances and Defects of Interest in Defects Detected on a Wafer

    公开(公告)号:US20190067060A1

    公开(公告)日:2019-02-28

    申请号:US16113930

    申请日:2018-08-27

    Abstract: Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.

    Metrology Guided Inspection Sample Shaping of Optical Inspection Results

    公开(公告)号:US20180321168A1

    公开(公告)日:2018-11-08

    申请号:US15671230

    申请日:2017-08-08

    Abstract: Information from metrology tools can be used during inspection or review with a scanning electron microscope. Metrology measurements of a wafer are interpolated and/or extrapolated over a field, which creates modified metrology data. The modified metrology data is associated with defect attributes from inspection measurements of a wafer. A wafer review sampling plan is generated based on the defect attributes and the modified metrology data. The wafer review sampling plan can be used during review of a wafer using the scanning electron microscope.

    Bonded Wafer Metrology
    5.
    发明申请

    公开(公告)号:US20180150952A1

    公开(公告)日:2018-05-31

    申请号:US15627834

    申请日:2017-06-20

    Abstract: Wafer edge profile images are analyzed at locations around a bonded wafer, which may have a top wafer and a carrier wafer. An offset curve is generated based on the wafer edge profile images. Displacement of the top wafer to the carrier wafer is determined based on the offset curve. The wafer edge profile images may be generated at multiple locations around the wafer. The wafer edge profile images may be shadowgram images. A system to determine displacement of the top wafer to the carrier wafer can include an imaging system connected with a controller.

    Using stochastic failure metrics in semiconductor manufacturing

    公开(公告)号:US10818001B2

    公开(公告)日:2020-10-27

    申请号:US16241467

    申请日:2019-01-07

    Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.

    Identifying nuisances and defects of interest in defects detected on a wafer

    公开(公告)号:US10699926B2

    公开(公告)日:2020-06-30

    申请号:US16113930

    申请日:2018-08-27

    Abstract: Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.

    USING STOCHASTIC FAILURE METRICS IN SEMICONDUCTOR MANUFACTURING

    公开(公告)号:US20200082523A1

    公开(公告)日:2020-03-12

    申请号:US16241467

    申请日:2019-01-07

    Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.

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