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1.发明授权Adaptive mode switching of flash memory address mapping based on host usage characteristics 有权基于主机使用特性的闪存地址映射的自适应模式切换公开(公告)号：US07631138B2
公开(公告)日：2009-12-08
申请号：US10750190
申请日：2003-12-30
申请人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
发明人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.
摘要翻译： 在诸如闪存EEPROM系统的非易失性存储器系统中，响应于主机编程和控制器数据合并模式，控制器将数据扇区映射到存储器的块和元区块的方式切换，以便提高性能和 减少磨损。 数据被编程到具有不同程度的并行性的存储器中。
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2.发明授权Method and structure for efficient data verification operation for non-volatile memories 有权用于非易失性存储器的有效数据验证操作的方法和结构公开(公告)号：US06972993B2
公开(公告)日：2005-12-06
申请号：US10360829
申请日：2003-02-07
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。 在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。 在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。 当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。 这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。 替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。 可以重复写入后验证，并使用不同的偏置条件读取数据。 该过程可以是自动的，也可以通过可以指定读取条件的命令执行。
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3.发明授权Adaptive mode switching of flash memory address mapping based on host usage characteristics 有权基于主机使用特性的闪存地址映射的自适应模式切换公开(公告)号：US08301826B2
公开(公告)日：2012-10-30
申请号：US12609789
申请日：2009-10-30
申请人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
发明人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.
摘要翻译： 在诸如闪存EEPROM系统的非易失性存储器系统中，响应于主机编程和控制器数据合并模式，控制器将数据扇区映射到存储器的块和元区块的方式切换，以便提高性能和 减少磨损。 数据被编程到具有不同程度的并行性的存储器中。
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公开(公告)号：US08117380B2
公开(公告)日：2012-02-14
申请号：US12433702
申请日：2009-04-30
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.
摘要翻译： 一种类型的非易失性存储器系统，其具有一起擦除的存储器单元的块，并且可以以每块的大量页面为单位从擦除状态编程。 如果要更新块的几页数据，则更新的页面被写入为此目的提供的另一个块。 然后，有效的原始和更新的数据在稍后的时间被组合，当这样做不影响存储器的性能时。 然而，如果要更新块的大量页面的数据，则更新的页面被写入未使用的擦除块，并且未改变的页面也被写入到相同的未使用的块。 通过不同的处理几页的更新，当进行小型更新时，内存性能得到改善。
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公开(公告)号：US08004895B2
公开(公告)日：2011-08-23
申请号：US12415158
申请日：2009-03-31
IPC分类号： G11C16/04
CPC分类号： G06F11/106 , G06F11/1068 , G11C8/08
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
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6.发明申请Adaptive Mode Switching of Flash Memory Address Mapping Based on Host Usage Characteristics 有权基于主机使用特性的闪存地址映射的自适应模式切换公开(公告)号：US20100049908A1
公开(公告)日：2010-02-25
申请号：US12609789
申请日：2009-10-30
申请人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
发明人： Carlos J. Gonzalez , Mark Sompel , Kevin M. Conley
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.
摘要翻译： 在诸如闪存EEPROM系统的非易失性存储器系统中，响应于主机编程和控制器数据合并模式，控制器将数据扇区映射到存储器的块和元区块的方式切换，以便提高性能和 减少磨损。 数据被编程到具有不同程度的并行性的存储器中。
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公开(公告)号：US08504798B2
公开(公告)日：2013-08-06
申请号：US10749831
申请日：2003-12-30
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.
摘要翻译： 一种类型的非易失性存储器系统，其具有一起擦除的存储器单元的块，并且可以以每块的大量页面为单位从擦除状态编程。 如果要更新块的几页数据，则更新的页面被写入为此目的提供的另一个块。 然后，有效的原始和更新的数据在稍后的时间被组合，当这样做不影响存储器的性能时。 然而，如果要更新块的大量页面的数据，则更新的页面被写入未使用的擦除块，并且未改变的页面也被写入到相同的未使用的块。 通过不同的处理几页的更新，当进行小型更新时，内存性能得到改善。
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8.发明授权Method and structure for efficient data verification operation for non-volatile memories 有权用于非易失性存储器的有效数据验证操作的方法和结构公开(公告)号：US07376011B2
公开(公告)日：2008-05-20
申请号：US11619991
申请日：2007-01-04
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。 在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。 在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。 当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。 这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。 替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。 可以重复写入后验证，并使用不同的偏置条件读取数据。 该过程可以是自动的，也可以通过可以指定读取条件的命令执行。
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公开(公告)号：US07012835B2
公开(公告)日：2006-03-14
申请号：US10678345
申请日：2003-10-03
IPC分类号： G11C19/08
CPC分类号： G06F11/106 , G06F11/1068 , G11C8/08
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
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10.发明授权Method and structure for reliable data copy operation for non-volatile memories 有权用于非易失性存储器的可靠数据复制操作的方法和结构公开(公告)号：US06266273B1
公开(公告)日：2001-07-24
申请号：US09643151
申请日：2000-08-21
IPC分类号： G11C1604
CPC分类号： G11C16/102 , G11C16/105
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit. When data are read from a flash array into a data register, the data is copied to a second register so that, during the ensuing program operation into the same array, the data may be transferred to the controller for the purpose of checking the data validity. This creates an improved performance system that doesn't suffer data transfer latency during copy operations but that is able to guarantee the validity of the data involved in such operations.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有数据寄存器和控制器电路的重复。 当将数据从闪存阵列读入数据寄存器时，数据被复制到第二寄存器，使得在随后的程序操作期间将数据传送到控制器以检查数据有效性 。 这创建了一个改进的性能系统，在复制操作期间不会遭受数据传输延迟，但是能够保证这些操作中涉及的数据的有效性。
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