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公开(公告)号：US08504798B2
公开(公告)日：2013-08-06
申请号：US10749831
申请日：2003-12-30
CPC分类号： G06F12/0246 , G06F2212/7202
摘要： A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.
摘要翻译： 一种类型的非易失性存储器系统，其具有一起擦除的存储器单元的块，并且可以以每块的大量页面为单位从擦除状态编程。 如果要更新块的几页数据，则更新的页面被写入为此目的提供的另一个块。 然后，有效的原始和更新的数据在稍后的时间被组合，当这样做不影响存储器的性能时。 然而，如果要更新块的大量页面的数据，则更新的页面被写入未使用的擦除块，并且未改变的页面也被写入到相同的未使用的块。 通过不同的处理几页的更新，当进行小型更新时，内存性能得到改善。
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2.发明授权Method and structure for efficient data verification operation for non-volatile memories 有权用于非易失性存储器的有效数据验证操作的方法和结构公开(公告)号：US07376011B2
公开(公告)日：2008-05-20
申请号：US11619991
申请日：2007-01-04
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。 在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。 在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。 当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。 这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。 替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。 可以重复写入后验证，并使用不同的偏置条件读取数据。 该过程可以是自动的，也可以通过可以指定读取条件的命令执行。
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公开(公告)号：US07012835B2
公开(公告)日：2006-03-14
申请号：US10678345
申请日：2003-10-03
IPC分类号： G11C19/08
CPC分类号： G06F11/106 , G06F11/1068 , G11C8/08
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
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4.发明授权Method and structure for reliable data copy operation for non-volatile memories 有权用于非易失性存储器的可靠数据复制操作的方法和结构公开(公告)号：US06266273B1
公开(公告)日：2001-07-24
申请号：US09643151
申请日：2000-08-21
IPC分类号： G11C1604
CPC分类号： G11C16/102 , G11C16/105
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit. When data are read from a flash array into a data register, the data is copied to a second register so that, during the ensuing program operation into the same array, the data may be transferred to the controller for the purpose of checking the data validity. This creates an improved performance system that doesn't suffer data transfer latency during copy operations but that is able to guarantee the validity of the data involved in such operations.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有数据寄存器和控制器电路的重复。 当将数据从闪存阵列读入数据寄存器时，数据被复制到第二寄存器，使得在随后的程序操作期间将数据传送到控制器以检查数据有效性 。 这创建了一个改进的性能系统，在复制操作期间不会遭受数据传输延迟，但是能够保证这些操作中涉及的数据的有效性。
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公开(公告)号：US20130042057A1
公开(公告)日：2013-02-14
申请号：US13586352
申请日：2012-08-15
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/0679 , G06F12/0893 , G06F2212/7201 , G06F2212/7203 , G11C14/0036 , G11C14/0045
摘要： A hybrid non-volatile system uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit their relative advantages. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the memory or read back to the host.
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公开(公告)号：US08050095B2
公开(公告)日：2011-11-01
申请号：US12945000
申请日：2010-11-12
IPC分类号： G11C16/04
CPC分类号： G06F11/106 , G06F11/1068 , G11C8/08
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.
摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。
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公开(公告)号：US20100023681A1
公开(公告)日：2010-01-28
申请号：US12572844
申请日：2009-10-02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/0679 , G06F12/0893 , G06F2212/7201 , G06F2212/7203 , G11C14/0036 , G11C14/0045
摘要： The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host.
摘要翻译： 本发明提出了一种混合非易失性系统，其使用基于两个或多个不同的非易失性存储器技术的非易失性存储器，以利用这些技术相对于其他技术的相对优点。 在示例性实施例中，存储器系统包括控制器和闪存，其中控制器具有基于诸如FeRAM的替代技术的非易失性RAM。 闪存用于存储用户数据，并且控制器中的非易失性RAM用于由控制器用于管理闪存中的主机数据的存储的系统控制数据。 在控制器中使用替代的非易失性存储器技术允许更快速地访问最近的控制数据的非易失性拷贝，因为它可以逐点更新。 在另一个示例性实施例中，备用非易失性存储器用作高速缓存，其中数据可以在其被写入存储器或读回主机之前安全地分级。
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公开(公告)号：US07173852B2
公开(公告)日：2007-02-06
申请号：US11253531
申请日：2005-10-18
IPC分类号： G11C11/34
CPC分类号： G06F11/106 , G06F11/1068 , G11C16/3418 , G11C16/3431 , G11C29/76
摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. Data is rewritten when severe errors are found during read operations. Portions of data are corrected and copied within the time limit for read operation. Corrected portions are written to dedicated blocks.
摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。 在读取操作期间发现严重错误时，数据被重写。 部分数据在读取操作的时限内得到纠正和复制。 校正的部分被写入专用块。
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公开(公告)号：US07120729B2
公开(公告)日：2006-10-10
申请号：US10686399
申请日：2003-10-14
CPC分类号： G11C29/76 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.
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10.发明授权Method and structure for efficient data verification operation for non-volatile memories 有权用于非易失性存储器的有效数据验证操作的方法和结构公开(公告)号：US06560143B2
公开(公告)日：2003-05-06
申请号：US10040748
申请日：2001-12-28
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations. The post-writer verification can be repeated and use different bias conditions for reading the data. The process can be automatic or executed by command that can specify the read conditions.
摘要翻译： 改进的基于闪存EEPROM存储器的存储子系统包括一个或多个闪存阵列，每个闪存阵列具有三个数据寄存器和一个控制器电路。 在闪存编程操作期间，使用一个数据寄存器来控制程序操作，第二个寄存器用于保存目标数据值，第三个寄存器用于加载下一个扇区的数据。 在闪存编程操作之后，将扇区的数据从闪存阵列读入第一数据寄存器并与存储在第二寄存器中的目标数据进行比较。 当数据验证良好时，来自第三寄存器的数据被复制到第一和第二寄存器用于下一个程序操作。 这创建了一个改进的性能系统，在程序操作完成后需要数据验证的程序操作期间不会遭受数据传输延迟。 替代实施例使用两个寄存器实现和单个寄存器实现来执行比较。 可以重复写入后验证，并使用不同的偏置条件读取数据。 该过程可以是自动的，也可以通过可以指定读取条件的命令执行。
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