-
公开(公告)号：US10748609B2
公开(公告)日：2020-08-18
申请号：US16606786
申请日：2018-04-10
Inventor： Rawan Naous , Khaled Nabil Salama
Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.
-
公开(公告)号：US10340001B2
公开(公告)日：2019-07-02
申请号：US15751650
申请日：2016-08-23
Inventor： Mohammed Affan Zidan , Hesham Omran , Rawan Naous , Ahmed Sultan Salem , Khaled Nabil Salama
Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and—calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.
-
公开(公告)号：US20180233196A1
公开(公告)日：2018-08-16
申请号：US15751650
申请日：2016-08-23
Inventor： Mohammed Affan Zidan , Hesham Omran , Rawan Naous , Ahmed Sultan Salem , Khaled Nabil Salama
CPC classification number: G11C13/004 , G11C13/0009 , G11C13/0033 , G11C2013/005 , G11C2013/0057 , G11C2213/70 , H01L27/2481 , H01L45/1206
Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and —calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.
-
-
Search Results
3
records
(took 0.015 seconds)
