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    Apparatus and method for controlling gradual conductance change in synaptic element
    1.
    发明授权
    Apparatus and method for controlling gradual conductance change in synaptic element 有权

    公开(公告)号：US12125527B2

    公开(公告)日：2024-10-22

    申请号：US17628280

    申请日：2020-07-30

    Applicant: Jun-sung Kim

    Inventor： Jun-sung Kim

    IPC: G11C11/00 ,  G06N3/065 ,  G06N3/08 ,  G11C11/16 ,  G11C11/54 ,  G11C13/00

    CPC classification number: G11C11/54 ,  G06N3/065 ,  G06N3/08 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/009

    Abstract: The present invention provides a memory apparatus capable of causing a gradual resistance change for information processing in an analog manner to a synaptic element for implementing a neuromorphic system. To this end, the present invention provides a memory apparatus including: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects, in the writing step, one or more memory cells from among the plurality of memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies, in the reading step, a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.
    The present invention also provides a method for determining a synaptic weight in a memory apparatus including a memory array including a plurality of memory cells capable of selectively storing logic states, bit lines and word lines connected to the plurality of memory cells, the method including: (a) selecting one or more memory cells from among the plurality of memory cells, and sequentially applying a writing voltage to write logic states therein; (b) applying a reading voltage to the one or more memory cells that has been selected to have the logic states written therein; and (c) determining, by the applied reading voltage, a synaptic weight through a sum of currents flowing through the one or more memory cells that has been selected to have the logic states written therein, wherein the selected one or more memory cells are recognized to operate as one synaptic element.

    Memory device and method for operating memory device
    3.
    发明授权
    Memory device and method for operating memory device 有权

    公开(公告)号：US10083746B2

    公开(公告)日：2018-09-25

    申请号：US15683876

    申请日：2017-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mu Hui Park

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/0064 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2213/72 ,  G11C2213/76

    Abstract: A memory device and a method for operating the memory device are provided. A resistive memory cell connected to a first node and configured to include a variable resistive element and an access element for controlling a current flowing through the variable resistive element. A detection circuit detects a threshold voltage of the access element and provides a detection current to a sensing node. A clamping circuit connected between the first node and the sensing node receives a first read voltage and ramps up a voltage of the first node. The first node is discharged by a discharge circuit when the detection current becomes equal to a bit line current flowing through the first node while the clamping circuit ramps up the voltage of the first node. A sense amplifier transitions an output voltage value when a voltage level of the sensing node becomes lower than a reference voltage.

    Systems and methods for managing read voltages in a cross-point memory array
    4.
    发明授权
    Systems and methods for managing read voltages in a cross-point memory array 有权

    公开(公告)号：US09842639B1

    公开(公告)日：2017-12-12

    申请号：US15288874

    申请日：2016-10-07

    Applicant: Kilopass Technology, Inc.

    Inventor： Frank Guo ,  Bruce Bateman

    IPC: G11C11/39

    CPC classification number: G11C11/39 ,  G11C13/0033 ,  G11C2013/005

    Abstract: Techniques are provided for managing voltages on memory cells in a cross-point array during a read operation. The techniques apply to vertical layer thyristor memory cells and non-thyristor memory cells. Voltages on selected bitlines (e.g., corresponding to memory cells from which data is to be read), are set to a read voltage level. Voltages on unselected bitlines (e.g., corresponding to memory cells from which data is not to be read and which are not to be disturbed) are set to a de-bias voltage level that is different from the read voltage level.

    Memory device
    8.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09368553B2

    公开(公告)日：2016-06-14

    申请号：US14624920

    申请日：2015-02-18

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Yoshiaki Asao

    IPC: H01L27/24 ,  G11C13/00 ,  H01L23/528 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0071 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.

    Abstract translation: 根据一个实施例，存储器件包括形成在衬底上的第一有源区，其在第三方向上延伸。 存储器件还包括设置在第一有源区上的三个栅电极，其在与第三方向相交的第二方向上延伸。 存储器件还包括至少两个或多个上层互连和至少两个或更多个下层互连，所述至少两个或更多个下层互连设置在第一有源区上，其沿与第二方向和第三方向相交的第一方向延伸。 存储器件还包括三个第一晶体管，它们中的每一个设置在第一有源区和三个栅电极之间的交点处。 存储器件还包括三个的第一晶体管是一个器件隔离晶体管和两个单元晶体管。

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20130148399A1

    公开(公告)日：2013-06-13

    申请号：US13764274

    申请日：2013-02-11

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Kenichi MUROOKA

    IPC: G11C5/02 ,  H01L45/00 ,  G11C13/00

    CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/004 ,  G11C2013/005 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/10 ,  H01L45/146 ,  H01L45/147

    Abstract: A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell.

    Abstract translation: 根据实施例的半导体存储器件包括多个第一字线，多个位线，电阻变化材料，多个第二字线和绝缘膜。 位线与第一个字线相交。 电阻变化材料设置在第一字线和位线的相应交点处。 第二个字线与位线相交。 绝缘膜设置在第二字线和位线的各个交叉处。 第一字线和第二字线之一之一被布置成夹住位线。 第二字线，位线和绝缘膜在第二字线和位线的各个交点配置场效应晶体管。 场效应晶体管和电阻变化材料配置一个存储单元。

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