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公开(公告)号:US20180166134A1
公开(公告)日:2018-06-14
申请号:US15735978
申请日:2016-06-15
Inventor: Mohammed Affan Zidan , Hesham Omran , Ahmed Sultan Salem , Khaled Nabil Salama
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/003 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2213/79
Abstract: A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.
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公开(公告)号:US10340001B2
公开(公告)日:2019-07-02
申请号:US15751650
申请日:2016-08-23
Inventor: Mohammed Affan Zidan , Hesham Omran , Rawan Naous , Ahmed Sultan Salem , Khaled Nabil Salama
Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and—calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.
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公开(公告)号:US10297318B2
公开(公告)日:2019-05-21
申请号:US15735978
申请日:2016-06-15
Inventor: Mohammed Affan Zidan , Hesham Omran , Ahmed Sultan Salem , Khaled Nabil Salama
Abstract: A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the method, the method includes selecting a row of a memristor array associated with a desired cell, measuring the value of the selected memristor row, and selecting a column of a memristor array associated with the desired cell. The selection of the column and selection of the row selects the desired cell. The method also includes measuring the value of the memristor selected row with the selected desired cell and determining the value of the desired cell based on the value of the selected memristor row and the value of the selected memristor row with the selected desired cell.
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公开(公告)号:US20180233196A1
公开(公告)日:2018-08-16
申请号:US15751650
申请日:2016-08-23
Inventor: Mohammed Affan Zidan , Hesham Omran , Rawan Naous , Ahmed Sultan Salem , Khaled Nabil Salama
CPC classification number: G11C13/004 , G11C13/0009 , G11C13/0033 , G11C2013/005 , G11C2013/0057 , G11C2213/70 , H01L27/2481 , H01L45/1206
Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and —calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout. In addition, these strategies consume an order of magnitude less power in comparison to alternative state-of-the-art readout techniques.
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