公开(公告)号：US20250124989A1

公开(公告)日：2025-04-17

申请号：US18814679

申请日：2024-08-26

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Yusuke ARAYASHIKI ,  Tsuyoshi OGIKUBO ,  Suzuka KAJIWARA ,  Motohiko FUJIMATSU ,  Katsuya NISHIYAMA ,  Kikuko SUGIMAE

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.

公开(公告)号：US20230253029A1

公开(公告)日：2023-08-10

申请号：US17842516

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Kikuko SUGIMAE ,  Katsuya NISHIYAMA ,  Yusuke ARAYASHIKI ,  Motohiko FUJIMATSU ,  Kyosuke SANO ,  Noboru SHIBATA

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/063

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

公开(公告)号：US20230024213A1

公开(公告)日：2023-01-26

申请号：US17960660

申请日：2022-10-05

Applicant: Kioxia Corporation

Inventor： Kikuko SUGIMAE ,  Yusuke ARAYASHIKI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US20220084609A1

公开(公告)日：2022-03-17

申请号：US17201332

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Kikuko SUGIMAE ,  Katsuya NISHIYAMA ,  Motohiko FUJIMATSU ,  Noboru SHIBATA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

公开(公告)号：US20240265984A1

公开(公告)日：2024-08-08

申请号：US18432269

申请日：2024-02-05

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Kikuko SUGIMAE ,  Yusuke ARAYASHIKI ,  Katsuya NISHIYAMA ,  Motohiko FUJIMATSU ,  Akiyuki MURAYAMA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26

Abstract: According to one embodiment, a memory device includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or larger). The sequencer is configured to execute a write operation having a loop process including a program operation and a verify operation. The program operation includes a first program process and a second program process. The sequencer is further configured to cause the first memory cell to store data by either the first program process or the second program process according to data to be written into the first memory cell in the write operation.