公开(公告)号：US08211785B2

公开(公告)日：2012-07-03

申请号：US11819776

申请日：2007-06-29

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层时，或者在源中的离子注入层形成离子注入层时，杂质掺杂过程中已经形成的晶体缺陷可以被充分地减小，以及 漏极区域。

公开(公告)号：US07279405B2

公开(公告)日：2007-10-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。

公开(公告)号：US07084068B2

公开(公告)日：2006-08-01

申请号：US10661564

申请日：2003-09-15

申请人： Kyoichi Suguro ,  Takayuki Ito ,  Takaharu Itani

发明人： Kyoichi Suguro ,  Takayuki Ito ,  Takaharu Itani

IPC分类号： H01L21/302 ,  H01L21/461 ,  C23C16/00

CPC分类号： H01L21/28185 ,  H01L21/02046 ,  H01L21/02233 ,  H01L21/02247 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/3144 ,  H01L21/32 ,  H01L21/67115 ,  H01L21/67155 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surface being made of quartz; a gas supply system configured to supply a gas required for a thermal processing on the substrate in parallel to a surface of the substrate; a transparent window located on an upper part of the processing chamber facing the susceptor; and a main heater configured to irradiate a pulsed light on the surface of the substrate to heat the substrate from the transparent window, the pulsed light having a pulse duration of approximately 0.1 ms to 200 ms and having a plurality of emission wavelengths.

摘要翻译： 一种退火炉，包括：配置成存储基板的处理室; 位于所述处理室中的基座，以便加载所述基板并具有用于在650℃以下加热所述基板的辅助加热器，所述基座具有由石英制成的表面; 气体供给系统，被配置为平行于所述基板的表面在所述基板上供给热处理所需的气体; 位于处理室的与感受器相对的上部的透明窗口; 以及主加热器，其被配置为在所述基板的表面上照射脉冲光以从所述透明窗加热所述基板，所述脉冲光具有约0.1ms至200ms的脉冲持续时间并且具有多个发射波长。

公开(公告)号：US20080260501A1

公开(公告)日：2008-10-23

申请号：US11819776

申请日：2007-06-29

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/677

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活这些杂质。 除了使用闪光灯FLA的最终光照射之外，光辐射的特征在于使用W卤素灯RTA或闪光灯FLA。 杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层或在源中的离子注入层形成离子注入层时，可以充分减少在杂质掺杂过程中发展的晶体缺陷，以及 漏极区域。

公开(公告)号：US20070243701A1

公开(公告)日：2007-10-18

申请号：US11783035

申请日：2007-04-05

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Takaharu Itani ,  Yoshihiko Saito

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Takaharu Itani ,  Yoshihiko Saito

IPC分类号： H01L21/425

CPC分类号： H01L21/2686 ,  H01L21/324 ,  H01L29/7833 ,  H01L29/7842

摘要： An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm−3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm−3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.

摘要翻译： 将杂质离子注入到具有体积微密度为5×10 -6至5×10 -7 cm -3以下的Si衬底的主表面中， 体积微观尺寸小于100nm，溶解氧浓度为1.1×10 18至1.2×10 -8 cm -3。 然后，Si衬底经历其加热/冷却速率高于1×10 5℃/秒的超快速热退火，从而电激活杂质以形成半导体的至少部分杂质扩散层 元件。

公开(公告)号：US20050124123A1

公开(公告)日：2005-06-09

申请号：US10980232

申请日：2004-11-04

申请人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Takaharu Itani ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L29/78 ,  F27B3/20 ,  F27B7/34 ,  F27B9/36 ,  H01L21/26 ,  H01L21/42 ,  H01L21/477

CPC分类号： H01L21/26533 ,  H01L21/324 ,  H01L29/6659

摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

摘要翻译： 通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。 通过光照射进行杂质掺杂后的退火。 这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射 。 杂质扩散可以被控制到最小，并且当在MOSFET的源极和漏极延伸区域中形成离子注入层时，在杂质掺杂过程中已经发展出的晶体缺陷可以被充分地减小，或者源中的离子注入层和 漏区。

公开(公告)号：US07989903B2

公开(公告)日：2011-08-02

申请号：US12757658

申请日：2010-04-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L21/02

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20100055859A1

公开(公告)日：2010-03-04

申请号：US12591085

申请日：2009-11-06

申请人： Takayuki Ito ,  Toshihiko Iinuma ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Toshihiko Iinuma ,  Kyoichi Suguro

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2686 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/6659

摘要： Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

摘要翻译： 公开了一种制造半导体器件的方法，包括将杂质元素的离子注入到半导体区域中，将作为IV族元素的预定元素或与杂质相同的导电类型的元素的离子注入半导体区域 元素，并且质量数大于杂质元素，并且用光照射杂质元素和预定元素被注入的区域以使该区域退火，该光具有发光强度分布，存在于a的分布的最大点 波长区域不大于600nm。

公开(公告)号：US07026205B2

公开(公告)日：2006-04-11

申请号：US10815931

申请日：2004-04-02

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823842

摘要： A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion, selectively implanting the second conductivity type impurity ions to the second gate electrode and the surface layer adjacent to the second insulating gate portion, after implanting the first and second conductivity types impurity ions, pre-annealing at a first substrate temperature, and after the pre-annealing, main-activating for the first and second types impurity ions at a second substrate temperature higher than the first substrate temperature for a treatment period shorter than a period of the pre-annealing.

摘要翻译： 一种半导体器件制造方法，其具有形成在半导体衬底上彼此间隔开的第一和第二绝缘栅极部分，选择性地将第一导电类型杂质离子注入到第一栅电极和与第一绝缘栅极部分相邻的半导体衬底的表面层 在将第一和第二导电类型的杂质离子注入到第二栅极电极和与第二绝缘栅极部分相邻的表面层之后，在第一衬底温度下进行预退火之后，以及在第一衬底温度之后，选择性地将第二导电型杂质离子注入 在第一衬底温度高于第一衬底温度的第二衬底温度下处理短于预退火周期的处理期间，对第一和第二类杂质离子进行主要激活。

公开(公告)号：US20050062107A1

公开(公告)日：2005-03-24

申请号：US10924909

申请日：2004-08-25

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/265 ,  H01L21/00 ,  H01L21/22 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L23/62

CPC分类号： H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor comprises a substrate including a single crystal semiconductor region, and a pattern including a line pattern provided on the substrate, the line pattern having a longitudinal direction differing from a crystal orientation of the single crystal semiconductor region.

摘要翻译： 半导体包括包括单晶半导体区域的衬底和包括设置在衬底上的线图案的图案，该线图案具有与单晶半导体区域的晶体取向不同的纵向方向。