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公开(公告)号：US10097192B2
公开(公告)日：2018-10-09
申请号：US15634373
申请日：2017-06-27
Applicant: MediaTek Inc.
Inventor： Jen-Huan Tsai
Abstract: Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance element, such as a resistor, configured to provide a desired reference voltage to the switched capacitor circuit. In some embodiments, a portion of the power absorbed by the impedance element may be recycled to power one or more additional circuit. Such additional circuit(s) may include active elements. In some embodiments, the switched capacitor circuit is part of an analog-to-digital converter. In some embodiments, the additional circuit(s) are also part of the analog-to-digital converter.
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公开(公告)号：US11626858B2
公开(公告)日：2023-04-11
申请号：US17196946
申请日：2021-03-09
Applicant: MediaTek Inc.
Inventor： Jen-Huan Tsai , Chih-Hong Lou
Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.
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公开(公告)号：US20170353192A1
公开(公告)日：2017-12-07
申请号：US15499872
申请日：2017-04-27
Applicant: MEDIATEK INC.
Inventor： Jen-Huan Tsai , Chih-Hong Lou
CPC classification number: H03M3/426 , H03M1/1245 , H03M1/466 , H03M3/338 , H03M3/37 , H03M3/412 , H03M3/424 , H03M3/458
Abstract: An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.
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公开(公告)号：US10979030B2
公开(公告)日：2021-04-13
申请号：US16044731
申请日：2018-07-25
Applicant: MEDIATEK Inc.
Inventor： Jen-Huan Tsai , Chih-Hong Lou
Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.
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公开(公告)号：US20180167077A1
公开(公告)日：2018-06-14
申请号：US15634373
申请日：2017-06-27
Applicant: MediaTek Inc.
Inventor： Jen-Huan Tsai
CPC classification number: H03M1/06 , H03M1/00 , H03M1/002 , H03M1/0678 , H03M1/12 , H03M1/38 , H03M1/745
Abstract: Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance element, such as a resistor, configured to provide a desired reference voltage to the switched capacitor circuit. In some embodiments, a portion of the power absorbed by the impedance element may be recycled to power one or more additional circuit. Such additional circuit(s) may include active elements. In some embodiments, the switched capacitor circuit is part of an analog-to-digital converter. In some embodiments, the additional circuit(s) are also part of the analog-to-digital converter.
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Patent Agency Ranking
公开(公告)号：US20210265982A1
公开(公告)日：2021-08-26
申请号：US17196946
申请日：2021-03-09
Applicant: MediaTek Inc.
Inventor： Jen-Huan Tsai , Chih-Hong Lou
Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.
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公开(公告)号：US20180175875A1
公开(公告)日：2018-06-21
申请号：US15603546
申请日：2017-05-24
Applicant: MEDIATEK Inc.
Inventor： Jen-Huan Tsai
CPC classification number: H03M1/1245 , H03M1/0626 , H03M1/468 , H03M3/426 , H03M3/458 , H03M3/47
Abstract: The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a comparator coupled to the main circuit. The main circuit may: transfer the input signal by an input transfer block, filter an error signal by a loop filter, and combine the transferred input signal and the filtered error signal to form a combined signal. The comparator may quantize the combined signal to provide the output signal, wherein the error signal may reflect a difference between the combined signal and the output signal.
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公开(公告)号：US09871534B2
公开(公告)日：2018-01-16
申请号：US15499872
申请日：2017-04-27
Applicant: MEDIATEK INC.
Inventor： Jen-Huan Tsai , Chih-Hong Lou
CPC classification number: H03M3/426 , H03M1/1245 , H03M1/466 , H03M3/338 , H03M3/37 , H03M3/412 , H03M3/424 , H03M3/458
Abstract: An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.
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公开(公告)号：US09473163B1
公开(公告)日：2016-10-18
申请号：US15060661
申请日：2016-03-04
Applicant: MEDIATEK Inc.
Inventor： Jen-Huan Tsai
CPC classification number: H03M1/466 , H03F3/45183 , H03F3/45237 , H03F2200/366
Abstract: A preamplifier circuit comprising six transistors is provided. The first transistor is coupled to a power supply line and the second transistor is coupled to a ground line. The first and second transistors are controlled by an enable signal. The third and fourth transistors are connected between the first and second transistors, for generating a first amplifier output signal in response to a first input signal. The fifth and sixth transistors are connected between the first and second transistors, for generating a second amplifier output signal in response to a second input signal. The first, third, and fifth transistors are of a first conductivity type, and the second, fourth, and sixth transistors are of a second conductivity type. The preamplifier circuit can be applied to any type of ADC that utilizes a comparator.
Abstract translation: 提供了包括六个晶体管的前置放大器电路。 第一晶体管耦合到电源线，而第二晶体管耦合到地线。 第一和第二晶体管由使能信号控制。 第三和第四晶体管连接在第一和第二晶体管之间，用于响应于第一输入信号产生第一放大器输出信号。 第五和第六晶体管连接在第一和第二晶体管之间，用于响应于第二输入信号产生第二放大器输出信号。 第一，第三和第五晶体管是第一导电类型，第二，第四和第六晶体管是第二导电类型。 前置放大器电路可以应用于使用比较器的任何类型的ADC。
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10.发明授权公开(公告)号：US10341148B2
公开(公告)日：2019-07-02
申请号：US16044749
申请日：2018-07-25
Applicant: MEDIATEK Inc.
Inventor： Jen-Huan Tsai
Abstract: The invention provides a sigma-delta modulator (SDM) and associated system improving spectrum efficiency of wired interconnection. The SDM may comprise a main circuit for transferring an aggregated signal by a signal transfer function, and a noise shaping circuit for shaping noise away from a low-pass band by a modified noise transfer function. A frequency response of the modified noise transfer function may have a notch at a passband, and the passband may not overlap with the low-pass band.
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