公开(公告)号：US20190068170A1

公开(公告)日：2019-02-28

申请号：US16044731

申请日：2018-07-25

Applicant: MEDIATEK Inc.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03H17/02 ,  H03M7/30 ,  H03H17/00 ,  H03H17/04

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

公开(公告)号：US09806725B2

公开(公告)日：2017-10-31

申请号：US15133369

申请日：2016-04-20

Applicant: MEDIATEK Inc.

Inventor： Yi-Jhan Sie ,  Po-Min Wang ,  Chih-Hong Lou

IPC: H03L7/093 ,  H03L7/099

CPC classification number: H03L7/093 ,  H03L7/085 ,  H03L7/099 ,  H03L7/197

Abstract: A PLL includes a phase frequency detector (PFD), a charge pump, a capacitor coupled to the charge pump, an analog-to-digital convertor (ADC), a noise canceller, an accumulator, a loop filter, an oscillator, a digital block and a frequency divider. The PFD detects a phase difference between a reference signal and a divided signal. The charge pump generates a charge pump signal in response to the phase difference. The ADC converts the charge pump signal to a first digital signal, and quantizes it to a second digital signal. The noise canceller forms a shaped noise signal according to the first and second digital signals, and eliminates the shaped noise signal at the output of the noise canceller to generate a noise cancelled signal. The accumulator accumulates the noise cancelled signal. The loop filter filters the accumulated signal. The oscillator provides an output oscillating signal in response to the filtered signal.

公开(公告)号：US09184730B2

公开(公告)日：2015-11-10

申请号：US14138557

申请日：2013-12-23

Applicant: MediaTek Inc.

Inventor： Chi Yun Wang ,  Chih-Hong Lou

IPC: H03F3/52 ,  H03H11/12 ,  H05B33/08 ,  H05B37/02

CPC classification number: H03H11/1217 ,  H05B33/0845 ,  H05B33/0854 ,  H05B37/0218 ,  Y02B20/46

Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.

Abstract translation: 提供了基于动态前馈OPAMP的电路。 第一放大级放大一对输入差分信号以提供一对中间差分信号。 第二放大级放大该对中间差分信号以提供一对输出差分信号。 第一电容器耦合到第一放大级的非反相输入端。 第二电容器耦合到第一放大级的反相输入端。 前馈跨导级耦合在第一和第二电容器与第二放大级之间。 第一和第二电容器和前馈级形成具有第一增益曲线的高频路径，并且第一放大级和第二放大级形成具有第二增益曲线的高增益路径。 运算放大器根据第一和第二增益曲线提供开环增益。

公开(公告)号：US20150171877A1

公开(公告)日：2015-06-18

申请号：US14540041

申请日：2014-11-13

Applicant: MEDIATEK INC.

Inventor： Yen-Chuan Huang ,  Chih-Hong Lou ,  Chi-Yun Wang ,  Li-Han Hung ,  Min-Hua Wu

IPC: H03M1/00 ,  H03M3/00 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/001 ,  H03M1/0626 ,  H03M1/46 ,  H03M3/344 ,  H03M3/37 ,  H03M3/438 ,  H03M3/458

Abstract: An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal.

Abstract translation: 模数转换装置包括：积分器，被配置为根据模拟输入信号和第一模拟反馈信号产生积分信号; 低通滤波器，被布置成根据积分信号产生第一滤波信号; 一个模数转换器，被配置成根据第一滤波信号产生数字输出信号; 以及第一数模转换器，被配置为根据数字输出信号产生第一模拟反馈信号。

公开(公告)号：US11626858B2

公开(公告)日：2023-04-11

申请号：US17196946

申请日：2021-03-09

Applicant: MediaTek Inc.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03H17/00 ,  H03H17/02 ,  H03H17/04 ,  H03M7/36 ,  H03M3/00 ,  H04B14/06 ,  H03M7/32

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

公开(公告)号：US11526186B2

公开(公告)日：2022-12-13

申请号：US17065445

申请日：2020-10-07

Applicant: MediaTek Inc.

Inventor： Po-Jung Chang ,  Yan-Jiun Chen ,  Chih-Hong Lou

IPC: G05F1/575

Abstract: A low-dropout regulator (LDO) capable of providing high power-supply rejection ratio (PSRR) and good reverse isolation. The LDO may include a core circuitry and a reverse isolation circuitry. The core circuitry may include a PSRR circuitry coupled to an output node and configured to provide high PSRR at the output node. The reverse isolation circuitry may be configured to provide good reverse isolation at the output node by, for example, providing current in response to ripples at the output node. The reverse isolation circuitry may be configured with bandwidth higher than that of the core circuitry such that it can provide fast transient response. The reverse isolation circuitry may be configurable and/or reconfigurable for a desirable reverse isolation performance. The reverse isolation circuitry may be configurable and/or reconfigurable to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

公开(公告)号：US20170353192A1

公开(公告)日：2017-12-07

申请号：US15499872

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M3/426 ,  H03M1/1245 ,  H03M1/466 ,  H03M3/338 ,  H03M3/37 ,  H03M3/412 ,  H03M3/424 ,  H03M3/458

Abstract: An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

公开(公告)号：US09484877B2

公开(公告)日：2016-11-01

申请号：US14467066

申请日：2014-08-25

Applicant: MEDIATEK INC.

Inventor： Chi-Yun Wang ,  Chih-Hong Lou ,  Yen-Chuan Huang ,  Li-Han Hung

IPC: H03F1/34 ,  H03G3/30 ,  H03F1/56 ,  H03F3/45 ,  H03B5/24

CPC classification number: H03G3/30 ,  H03B5/24 ,  H03F1/56 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45118 ,  H03F2203/45526

Abstract: A resonating device includes: an amplifying circuit having a first input terminal, and an output terminal for outputting an output signal; a first feedback circuit coupled between the first input terminal and the output terminal of the amplifying circuit; a second feedback circuit, coupled between the first input terminal and the output terminal of the amplifying circuit; and a gain adjusting circuit, having an input terminal for receiving an input signal, and a first output terminal coupled to the first input terminal of the amplifying circuit; wherein a first equivalent impedance on a first intermediate terminal in the first feedback circuit substantially equals a second equivalent impedance on a second intermediate terminal in the second feedback circuit, and the gain adjusting circuit is arranged to tune a transfer function from the input signal to the output signal.

Abstract translation: 谐振装置包括：具有第一输入端的放大电路和用于输出输出信号的输出端; 耦合在放大电路的第一输入端和输出端之间的第一反馈电路; 耦合在放大电路的第一输入端和输出端之间的第二反馈电路; 以及增益调整电路，具有用于接收输入信号的输入端子和耦合到放大电路的第一输入端子的第一输出端子; 其中所述第一反馈电路中的第一中间端子上的第一等效阻抗基本上等于所述第二反馈电路中的第二中间端子上的第二等效阻抗，并且所述增益调整电路被布置成将传递函数从所述输入信号调谐到 输出信号。

公开(公告)号：US09184754B2

公开(公告)日：2015-11-10

申请号：US14540041

申请日：2014-11-13

Applicant: MEDIATEK INC.

Inventor： Yen-Chuan Huang ,  Chih-Hong Lou ,  Chi-Yun Wang ,  Li-Han Hung ,  Min-Hua Wu

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/06 ,  H03M3/00 ,  H03M1/46

CPC classification number: H03M1/001 ,  H03M1/0626 ,  H03M1/46 ,  H03M3/344 ,  H03M3/37 ,  H03M3/438 ,  H03M3/458

Abstract: An analog-to-digital converting device includes: an integrator arranged to generate an integrating signal according to an analog input signal and a first analog feedback signal; a low-pass filter arranged to generate a first filtered signal according to the integrating signal; an analog-to-digital converter arranged to generate a digital output signal according to the first filtered signal; and a first digital-to-analog converter arranged to generate the first analog feedback signal according to the digital output signal.

Abstract translation: 模数转换装置包括：积分器，被配置为根据模拟输入信号和第一模拟反馈信号产生积分信号; 低通滤波器，被布置成根据积分信号产生第一滤波信号; 一个模数转换器，被配置成根据第一滤波信号产生数字输出信号; 以及第一数模转换器，被配置为根据数字输出信号产生第一模拟反馈信号。

公开(公告)号：US20150171811A1

公开(公告)日：2015-06-18

申请号：US14541113

申请日：2014-11-13

Applicant: MEDIATEK INC.

Inventor： Min-Hua Wu ,  Chih-Hong Lou ,  Yen-Chuan Huang ,  Chi-Yun Wang

IPC: H03G3/00 ,  H03F3/45 ,  H03G3/30

CPC classification number: H03F3/45076 ,  H03F2200/222 ,  H03F2200/234 ,  H03F2203/45151 ,  H03F2203/45576 ,  H03G1/0088 ,  H03M1/742

Abstract: A current controlling device includes: a first resistive circuit arranged to selectively conduct a first current to a first output terminal from a first input terminal; and a second resistive circuit arranged to selectively conduct a second current to a second output terminal from the first input terminal; wherein when the first resistive circuit conducts the first current to the first output terminal and when the second resistive circuit does not conduct the second current to the second output terminal, the first input terminal has a first input impedance; when the first resistive circuit does not conduct the first current to the first output terminal and when the second resistive circuit conducts the second current to the second output terminal, the first input terminal has a second input impedance substantially equal to the first input impedance.

Abstract translation: 电流控制装置包括：第一电阻电路，布置成选择性地将第一电流从第一输入端子传导到第一输出端子; 以及第二电阻电路，布置成从第一输入端子选择性地将第二电流传导到第二输出端子; 其中当所述第一电阻电路将所述第一电流传导到所述第一输出端时，并且当所述第二电阻电路不将所述第二电流传导到所述第二输出端时，所述第一输入端具有第一输入阻抗; 当第一电阻电路不向第一输出端子传导第一电流，并且当第二电阻电路将第二电流传导到第二输出端时，第一输入端具有基本上等于第一输入阻抗的第二输入阻抗。