公开(公告)号：US09876501B2

公开(公告)日：2018-01-23

申请号：US14267929

申请日：2014-05-02

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Hsiang-Hui Chang

IPC: H03F3/217 ,  H03K19/0175 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

公开(公告)号：US09118371B2

公开(公告)日：2015-08-25

申请号：US14281916

申请日：2014-05-20

Applicant: MEDIATEK INC.

Inventor： Chi-Hsueh Wang ,  Yang-Chuan Chen ,  Hsiang-Hui Chang ,  Li-Shin Lai ,  Khurram Muhammad

IPC: H04K1/02 ,  H04B1/04 ,  H04L25/08 ,  H03F3/217 ,  H03F3/24 ,  H03G3/00

CPC classification number: H04B1/0475 ,  H03F1/02 ,  H03F3/2178 ,  H03F3/24 ,  H03G3/002 ,  H04B2001/045 ,  H04L25/08

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract translation: 数字发射机包括：多个转换装置，被配置为根据多个数字输入信号产生多个转换信号; 补偿装置，被配置为根据所述多个数字输入信号生成至少一个补偿信号; 以及组合电路，被配置为根据所述多个转换信号和所述至少一个补偿信号输出放大的输出信号。

公开(公告)号：US09917586B2

公开(公告)日：2018-03-13

申请号：US15611822

申请日：2017-06-02

Applicant: MediaTek Inc.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20 ,  H03F1/02 ,  H03F3/24

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US09698785B2

公开(公告)日：2017-07-04

申请号：US15255159

申请日：2016-09-02

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US20140347127A1

公开(公告)日：2014-11-27

申请号：US14267929

申请日：2014-05-02

Applicant: Mediatek Inc.

Inventor： Yang-Chuan Chen ,  Hsiang-Hui Chang

IPC: H03F3/217

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

Abstract translation: 开关功率放大器包括：由第一数字信号控制的第一晶体管，以选择性地输出第一输出信号; 由第二数字信号控制的第二晶体管，以选择性地输出第二输出信号; 以及控制电路，被配置为根据第一数字信号和第三数字信号产生第二数字信号; 其中所述第一输出信号和所述第二输出信号在所述第一晶体管和所述第二晶体管的公共连接的节点上输出。

公开(公告)号：US20170272074A1

公开(公告)日：2017-09-21

申请号：US15611822

申请日：2017-06-02

Applicant: MediaTek Inc.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H03K19/0175 ,  H03F3/217 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L27/20 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/34 ,  H04L25/08

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

公开(公告)号：US09425796B2

公开(公告)日：2016-08-23

申请号：US14272522

申请日：2014-05-08

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chih-Jung Chen ,  Hsiang-Hui Chang

IPC: H04L27/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.

Abstract translation: 数据转换装置包括：数据采样电路，被配置为对数字信号进行上采样以根据时钟信号产生上采样信号; 电压电平发生电路，被布置成产生可调电压; 以及信号转换电路，被配置为根据可调电压和上采样信号产生转换信号。

公开(公告)号：US09191004B2

公开(公告)日：2015-11-17

申请号：US14271470

申请日：2014-05-07

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen

IPC: H04L27/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  H04L7/00 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A signal converting device includes: a first converting circuit arranged to receive a first inputting signal; and a first capacitive circuit coupled between an output terminal of the first converting circuit and a reference voltage; wherein the first converting circuit is arranged to generate a first converting signal on the output terminal of the first converting circuit according to the first inputting signal.

Abstract translation: 信号转换装置包括：第一转换电路，被布置成接收第一输入信号; 以及耦合在所述第一转换电路的输出端子与参考电压之间的第一电容电路; 其中，所述第一转换电路被配置为根据所述第一输入信号在所述第一转换电路的输出端产生第一转换信号。

公开(公告)号：US20140348279A1

公开(公告)日：2014-11-27

申请号：US14273547

申请日：2014-05-09

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract translation: 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。

公开(公告)号：US09577638B2

公开(公告)日：2017-02-21

申请号：US14273547

申请日：2014-05-09

Applicant: MEDIATEK INC.

Inventor： Yang-Chuan Chen ,  Chi-Hsueh Wang ,  Hsiang-Hui Chang ,  Bo-Yu Lin

IPC: H04L7/00 ,  H03K19/0175 ,  H03F3/217 ,  H04L27/34 ,  H04B1/04 ,  H04W24/02 ,  H04L25/02 ,  H04L25/08 ,  H03M1/12 ,  G01R21/06 ,  G01R23/00 ,  H03F1/24 ,  H04L27/20

CPC classification number: H03K19/017509 ,  G01R21/06 ,  G01R23/00 ,  H03F1/02 ,  H03F1/24 ,  H03F3/2178 ,  H03F3/24 ,  H03F2203/21154 ,  H03K19/017581 ,  H03M1/12 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0408 ,  H04B2001/045 ,  H04L7/0037 ,  H04L7/0091 ,  H04L25/028 ,  H04L25/08 ,  H04L27/2053 ,  H04L27/2067 ,  H04L27/3411 ,  H04L27/3444 ,  H04W24/02

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract translation: 数字信号上变换装置包括：时钟发生电路，被配置为产生参考时钟信号; 调整电路，耦合到所述时钟发生电路，并且被配置为根据所述参考时钟信号产生第一时钟信号和第二时钟信号; 耦合到所述调整电路的基带电路，用于接收所述第一时钟信号，其中所述基带电路还根据所述第一时钟信号产生数字输出信号; 以及耦合到所述调整电路和所述基带电路的采样电路，用于接收所述第二时钟信号和所述数字输出信号，其中所述第二时钟信号和所述数字输出信号是不重叠的; 其中所述采样电路基于所述第二时钟信号对所述数字输出信号进行采样，然后组合所述采样的数字输出信号，以便产生组合的数字信号。