公开(公告)号：US20160139655A1

公开(公告)日：2016-05-19

申请号：US14931923

申请日：2015-11-04

Applicant: MediaTek Inc.

Inventor： Jia-Ming CHEN ,  Hung-Lin CHOU ,  Pi-Cheng HSIAO ,  Ya-Ting CHANG ,  Yun-Ching LI ,  Yu-Ming LIN

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/5088 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Abstract translation: 能源效率在多集群系统中进行管理。 该系统检测活动集群的当前工作频率进入或跨越活动集群的一个或多个预定频率点中的任何一个的事件，其中主动集群包括一个或多个第一处理器核心。 当检测到事件时，系统执行以下步骤：（1）识别包括一个或多个第二处理器核心的目标群集，其中第一群集中的每个第一处理器核心和第二群集中的每个第二处理器核心具有不同的能量 效率特性; （2）激活所述第二集群中的至少一个第二处理器核心; （3）确定是否将来自所述第一集群的一个或多个中断请求迁移到所述第二集群; 以及（4）基于性能和功率需求确定是否去活动所述活动集群的至少一个第一处理器核心。

公开(公告)号：US20180332252A1

公开(公告)日：2018-11-15

申请号：US15806718

申请日：2017-11-08

Applicant: MEDIATEK INC.

Inventor： Wei-Ting WANG ,  Han-Lin LI ,  Yu-Jen CHEN ,  Yu-Ming LIN

IPC: H04N7/01

CPC classification number: H04N7/0127 ,  G09G5/005 ,  G09G2340/0435 ,  G09G2350/00 ,  G09G2360/08

Abstract: An image processing apparatus including first circuitry, second circuitry, third circuitry, and fourth circuitry is provided. The first circuitry determines a frame miss rate according to a current frame rate and a target frame rate of an image signal. The second circuitry decreases the target frame rate to the current frame rate when the frame miss rate is greater than a first threshold. The third circuitry increases the target frame rate to an upper-limit frame rate which is determined according to the frame rendering time or memory bandwidth capability, when the frame miss rate is less than a second threshold which is smaller than the first threshold. The fourth circuitry applies the decreased or increased target frame rate for an image to be displayed.

公开(公告)号：US20180074857A1

公开(公告)日：2018-03-15

申请号：US15817819

申请日：2017-11-20

Applicant: MEDIATEK INC.

Inventor： Ya-Ting CHANG ,  Yu-Ting CHEN ,  Yu-Ming LIN ,  Jia-Ming CHEN ,  Hung-Lin CHOU ,  Tzu-Jen LO

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/483

Abstract: A multi-core processor system and method are provided. The multi-core processor system includes a plurality of processor cores and a task scheduler. The processor cores perform a plurality of tasks, wherein each of the tasks is in a respective one of a plurality of scheduling classes. The task scheduler obtains first task assignment information about tasks which are in a first scheduling class from the scheduling classes and assigned to the processor cores, obtains second task assignment information about tasks in one or more other scheduling classes and assigned to the processor cores, and refers to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores. Prior to the assigning the runnable task, the runnable task has been assigned to one of the processor cores.

公开(公告)号：US20160327999A1

公开(公告)日：2016-11-10

申请号：US15107984

申请日：2015-09-17

Applicant: MEDIATEK INC.

Inventor： Ya-Ting CHANG ,  Lee-Kee YONG ,  Shih-Yen CHIU ,  Ming-Hsien LEE ,  Jia-Ming CHEN ,  Yu-Ming LIN ,  Hung-Lin CHOU ,  Tzu-Jen LO ,  Koon Woon SOON

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/20 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract translation: 具有多个处理器内核的计算系统通过动态频率缩放来管理功耗和性能。 当一个或多个集群内的活动处理器核心总数小于预定数量时，系统检测到状态，并且活动处理器核心的工作频率已经升高到指定的最高频率。 该系统还获得一个或多个簇的环境温度测量。 在检测到状况时，系统会根据环境温度测量值将工作频率提高到高于规定的最高频率，同时保持与主动处理器内核相同的电源电压。

公开(公告)号：US20160210460A1

公开(公告)日：2016-07-21

申请号：US14812243

申请日：2015-07-29

Applicant: MediaTek Inc.

Inventor： Wen-Long YANG ,  Jia-Ming CHEN ,  Ming-Yueh CHUANG ,  Nicholas Ching Hui TANG ,  Yu-Ming LIN

IPC: G06F21/60 ,  G06F17/30

CPC classification number: G06F21/78 ,  G06F17/30088

Abstract: A method for operating an electronic device, and an electronic device, are provided. In the normal operation state of the electronic device, data which is stored in the main storage device of the electronic device is encrypted by a first encryption algorithm prior to being stored in a non-volatile storage device of the electronic device. The method includes the steps of generating snapshot data in the main storage device when the electronic device is entering a hibernation state, allocating space in the non-volatile storage device for storing the snapshot data, and storing the snapshot data in the space without encrypting the snapshot data using the first encryption algorithm.

Abstract translation: 提供一种操作电子设备的方法和电子设备。 在电子设备的正常操作状态下，存储在电子设备的主存储设备中的数据在被存储在电子设备的非易失性存储设备中之前由第一加密算法加密。 该方法包括以下步骤：当电子设备进入休眠状态时在主存储设备中生成快照数据，在非易失性存储设备中分配用于存储快照数据的空间，以及将快照数据存储在空间中，而不加密 快照数据使用第一个加密算法。

公开(公告)号：US20160139964A1

公开(公告)日：2016-05-19

申请号：US14936686

申请日：2015-11-10

Applicant: MediaTek Inc.

Inventor： Jia-Ming CHEN ,  Hung-Lin CHOU ,  Ya-Ting CHANG ,  Shih-Yen CHIU ,  Chia-Hao HSU ,  Yu-Ming LIN ,  Wan-Ching HUANG ,  Jen-Chieh YANG ,  Pi-Cheng HSIAO

IPC: G06F9/50 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F2209/505 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Abstract translation: 具有不同能量效率特性的处理器核心的多集群系统被配置为以高效率运行，从而可以满足性能和功率要求。 该系统包括组中层次结构中的多个处理器核心。 组的层次结构包括：多个一级组，每个一级组，包括具有相同能量效率特性的一个或多个处理器核心，以及被配置为由一级调度器分配任务的每个一级组; 一个或多个2级组，每个2级组包括相应的1级组，具有不同能量效率特性的相同2级组的不同级别1组中的处理器核心，以及被配置为 由相应的二级调度程序分配任务; 以及包括一个或多个2级组并被配置为由3级调度器分配任务的3级组。