中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.016 seconds)

    Offloading execution of a multi-task parameter-dependent operation to a network device
    2.
    发明申请
    Offloading execution of a multi-task parameter-dependent operation to a network device 有权

    公开(公告)号：US20230089099A1

    公开(公告)日：2023-03-23

    申请号：US18071692

    申请日：2022-11-30

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Roman Nudelman ,  Gil Bloch ,  Daniel Marcovitch

    IPC: G06F9/48 ,  G06F9/30 ,  G06F9/54

    Abstract: A processing device includes an interface and one or more processing circuits. The interface is to connect to a host processor. The one or more processing circuits are to receive from the host processor, via the interface, a notification specifying an operation for execution by the processing device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks, in response to the notification, to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation in accordance with the schedule.

    SYSTEM AND METHOD FOR LOW LATENCY PACKET PROCESSING
    4.
    发明申请
    SYSTEM AND METHOD FOR LOW LATENCY PACKET PROCESSING 有权

    公开(公告)号：US20250028658A1

    公开(公告)日：2025-01-23

    申请号：US18224262

    申请日：2023-07-20

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

    IPC: G06F13/16 ,  G06F9/54

    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

    Offloading execution of a multi-task parameter-dependent operation to a network device
    6.
    发明申请
    Offloading execution of a multi-task parameter-dependent operation to a network device 有权

    公开(公告)号：US20220188147A1

    公开(公告)日：2022-06-16

    申请号：US17120321

    申请日：2020-12-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Roman Nudelman ,  Gil Bloch ,  Daniel Marcovitch

    IPC: G06F9/48 ,  G06F9/54 ,  G06F9/30

    Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.

    Patterned Remote Direct Memory Access (RDMA)
    9.
    发明公开
    Patterned Remote Direct Memory Access (RDMA) 审中-公开

    公开(公告)号：US20240015217A1

    公开(公告)日：2024-01-11

    申请号：US17858097

    申请日：2022-07-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

    IPC: H04L67/1097

    CPC classification number: H04L67/1097

    Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

    STRIDED MESSAGE BASED RECEIVE BUFFER
    10.
    发明申请
    STRIDED MESSAGE BASED RECEIVE BUFFER 有权

    公开(公告)号：US20250030649A1

    公开(公告)日：2025-01-23

    申请号：US18224258

    申请日：2023-07-20

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

    IPC: H04L49/9057

    Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.

Patent Agency Ranking