公开(公告)号：US12216575B2

公开(公告)日：2025-02-04

申请号：US17858104

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F12/06 ,  G06F12/0831 ,  G06F13/40 ,  G06F15/173

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

公开(公告)号：US20250028658A1

公开(公告)日：2025-01-23

申请号：US18224262

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: G06F13/16 ,  G06F9/54

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

公开(公告)号：US20250023668A1

公开(公告)日：2025-01-16

申请号：US18351544

申请日：2023-07-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roee Moyal ,  Gil Kremer ,  Ortal Ben Moshe ,  Ariel Shahar

IPC: H04L1/1607 ,  H04L1/08 ,  H04L47/34

Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.

公开(公告)号：US20240012773A1

公开(公告)日：2024-01-11

申请号：US17858102

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US20240007548A1

公开(公告)日：2024-01-04

申请号：US17855362

申请日：2022-06-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Aviv Kfir ,  Ortal Ben Moshe ,  Barak Gafni

IPC: H04L69/22 ,  H04L45/50 ,  H04L12/46

CPC classification number: H04L69/22 ,  H04L45/50 ,  H04L12/4633

Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a packet parser and a state machine that includes a NULL header state. The packet parser references the state machine to enter the NULL header state automatically in response to parsing a packet header of a predetermined type and then, while in the NULL header state, analyzes a subsequent set of bytes without advancing a parser pointer.

公开(公告)号：US20250030649A1

公开(公告)日：2025-01-23

申请号：US18224258

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: H04L49/9057

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.

公开(公告)号：US12107943B2

公开(公告)日：2024-10-01

申请号：US17855362

申请日：2022-06-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Aviv Kfir ,  Ortal Ben Moshe ,  Barak Gafni

IPC: H04L69/22 ,  H04L12/46 ,  H04L45/50

CPC classification number: H04L69/22 ,  H04L12/4633 ,  H04L45/50

Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a packet parser and a state machine that includes a NULL header state. The packet parser references the state machine to enter the NULL header state automatically in response to parsing a packet header of a predetermined type and then, while in the NULL header state, analyzes a subsequent set of bytes without advancing a parser pointer.

公开(公告)号：US20240012753A1

公开(公告)日：2024-01-11

申请号：US17858104

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F12/06 ,  G06F12/0831 ,  G06F15/173 ,  G06F13/40

CPC classification number: G06F12/0653 ,  G06F12/0835 ,  G06F15/17331 ,  G06F13/4027

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

公开(公告)号：US12137141B2

公开(公告)日：2024-11-05

申请号：US17858097

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: H04L12/70 ,  H04L41/0806 ,  H04L67/1097 ,  H04L67/12 ,  H04W48/08

Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US12135662B2

公开(公告)日：2024-11-05

申请号：US17858102

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F13/28

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.