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公开(公告)号：US20220021393A1
公开(公告)日：2022-01-20
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US11637557B2
公开(公告)日：2023-04-25
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号：US11171816B2
公开(公告)日：2021-11-09
申请号：US16943615
申请日：2020-07-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Matan Groen , Chen Gaist , Hananel Faig
Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.
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公开(公告)号：US11283454B2
公开(公告)日：2022-03-22
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US20220173741A1
公开(公告)日：2022-06-02
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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Patent Agency Ranking
公开(公告)号：US20200169379A1
公开(公告)日：2020-05-28
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US09344117B2
公开(公告)日：2016-05-17
申请号：US13839193
申请日：2013-03-15
Applicant: Mellanox Technologies Ltd.
Inventor： Liron Mula , Ran Ravid , Chen Gaist , Omer Sella , Oren Tzvi Sela
CPC classification number: H03M13/1515 , H03M13/153 , H03M13/1575 , H03M13/3715
Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.
Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。
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公开(公告)号：US20210044461A1
公开(公告)日：2021-02-11
申请号：US16943615
申请日：2020-07-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Matan Groen , Chen Gaist , Hananel Faig
Abstract: A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N′
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公开(公告)号：US10778406B2
公开(公告)日：2020-09-15
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US20140281840A1
公开(公告)日：2014-09-18
申请号：US13839193
申请日：2013-03-15
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Liron Mula , Ran Ravid , Chen Gaist , Omer Sela , Oren Tzvi Sela
IPC: H03M13/15
CPC classification number: H03M13/1515 , H03M13/153 , H03M13/1575 , H03M13/3715
Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.
Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。
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