公开(公告)号：US20240370074A1

公开(公告)日：2024-11-07

申请号：US18309842

申请日：2023-05-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Amit Kazimirsky ,  Eyal Srebro ,  Niv Aibester ,  George Elias

IPC: G06F1/3206

Abstract: A device includes one or more ports, one or more bandwidth shapers, and processing logic. The one or more ports are to connect to a communication network. A given bandwidth shaper is to: (i) when disabled, output traffic at an available full data rate, and (ii) when enabled, output the traffic at a specified shaper data rate lower than the available full data rate. The processing logic is to receive or generate notifications, which are indicative of average power that is consumed by the network device while outputting traffic through the one or more bandwidth shapers via the one or more ports, and based on at least some of the notifications, toggle at least one of the one or more bandwidth shapers between being enabled and disabled, to retain the average power consumed below a specified power budget.

公开(公告)号：US20150263994A1

公开(公告)日：2015-09-17

申请号：US14207680

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Noam Katz Abramovich ,  George Elias ,  Ido Bukspan ,  Benny Koren ,  Gil Bloch

IPC: H04L12/861 ,  H04L12/803 ,  H04L12/801

CPC classification number: H04L49/90 ,  H04L47/115 ,  H04L47/122 ,  H04L47/18 ,  H04L47/283 ,  H04L47/30 ,  H04L49/3036

Abstract: A switching apparatus includes multiple ports, each including a respective buffer, and a switch controller. The switch controller is configured to concatenate the buffers of at least an input port and an output port selected from among the multiple ports for buffering traffic of a long-haul link, which is connected to the input port and whose delay exceeds buffering capacity of the buffer of the input port alone, and to carry out end-to-end flow control for the long haul link between the output port and the input port.

Abstract translation: 开关装置包括多个端口，每个端口包括相应的缓冲器和开关控制器。 交换机控制器被配置为连接至少一个输入端口和从多个端口中选择的输出端口的缓冲器，用于缓冲连接到输入端口并且其延迟超过缓冲容量的长途链路的流量 单独输入端口的缓冲区，并为输出端口和输入端口之间的长途链路执行端到端流控制。

公开(公告)号：US20230036954A1

公开(公告)日：2023-02-02

申请号：US17385962

申请日：2021-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Shahaf Shuler ,  George Elias ,  Nizan Atias ,  Adi Maymon

IPC: G06F12/14 ,  G06F12/02 ,  G06F9/30

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

公开(公告)号：US10998032B2

公开(公告)日：2021-05-04

申请号：US16268507

申请日：2019-02-06

Applicant: Mellanox Technologies, Ltd.

Inventor： George Elias ,  Hillel Chapman ,  Eitan Zahavi ,  Elad Mentovich

IPC: G11C11/406

Abstract: One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.

公开(公告)号：US09325641B2

公开(公告)日：2016-04-26

申请号：US14207680

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Noam Katz Abramovich ,  George Elias ,  Ido Bukspan ,  Benny Koren ,  Gil Bloch

IPC: H04L12/861 ,  H04L12/801 ,  H04L12/803

CPC classification number: H04L49/90 ,  H04L47/115 ,  H04L47/122 ,  H04L47/18 ,  H04L47/283 ,  H04L47/30 ,  H04L49/3036

Abstract: A switching apparatus includes multiple ports, each including a respective buffer, and a switch controller. The switch controller is configured to concatenate the buffers of at least an input port and an output port selected from among the multiple ports for buffering traffic of a long-haul link, which is connected to the input port and whose delay exceeds buffering capacity of the buffer of the input port alone, and to carry out end-to-end flow control for the long haul link between the output port and the input port.

Abstract translation: 开关装置包括多个端口，每个端口包括相应的缓冲器和开关控制器。 交换机控制器被配置为连接至少一个输入端口和从多个端口中选择的输出端口的缓冲器，用于缓冲连接到输入端口并且其延迟超过缓冲容量的长途链路的流量 单独输入端口的缓冲区，并为输出端口和输入端口之间的长途链路执行端到端流控制。

公开(公告)号：US20150103667A1

公开(公告)日：2015-04-16

申请号：US14052743

申请日：2013-10-13

Applicant: Mellanox Technologies Ltd.

Inventor： George Elias ,  Eyal Srebro ,  Ido Bukspan ,  Itamar Rabenstein ,  Ran Ravid ,  Barak Gafni ,  Anna Saksonov

IPC: H04L12/801

CPC classification number: H04L47/30 ,  H04L47/11 ,  H04L47/12

Abstract: A method in a communication network includes defining a root congestion condition for a network switch if the switch creates congestion in the network while switches downstream are congestion free, and a victim congestion condition if the switch creates the congestion as a result of one or more other congested switches downstream. A buffer fill level in a first switch, created by network traffic, is monitored. A binary notification is received from a second switch, which is connected to the first switch. A decision whether the first switch or the second switch is in a root or a victim congestion condition is made, based on both the buffer fill level and the binary notification. A network congestion control procedure is applied based on the decided congestion condition.

Abstract translation: 通信网络中的一种方法包括：如果交换机在网络中产生拥塞，而下游的交换机拥塞不足则定义网络交换机的根拥塞状况;以及如果交换机由于一个或多个其他 下游拥塞交换机。 监视由网络流量创建的第一交换机中的缓冲区填充级别。 从连接到第一开关的第二开关接收二进制通知。 基于缓冲器填充级别和二进制通知，进行第一交换机或第二交换机是否处于根或者拥塞状态的判定。 基于确定的拥塞状况应用网络拥塞控制过程。

公开(公告)号：US11580036B1

公开(公告)日：2023-02-14

申请号：US17385962

申请日：2021-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Shahaf Shuler ,  George Elias ,  Nizan Atias ,  Adi Maymon

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02

Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

公开(公告)号：US10462075B2

公开(公告)日：2019-10-29

申请号：US15470940

申请日：2017-03-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/879 ,  H04L12/861

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US09641465B1

公开(公告)日：2017-05-02

申请号：US13972968

申请日：2013-08-22

Applicant: Mellanox Technologies Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/861

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9094

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US20240406122A1

公开(公告)日：2024-12-05

申请号：US18203227

申请日：2023-05-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Matari ,  Matisyahu Meier Goldmeier ,  George Elias ,  Ofir Klara Altshul ,  Itamar Rabenstein ,  Noam Michaelis ,  Eyal Srebro

IPC: H04L49/101 ,  H04L49/00 ,  H04L49/253

Abstract: An apparatus includes a crossbar circuit that routes one or more packets between one or more ingress domains and one or more egress domains. The crossbar circuit includes sub-crossbar domains. An ingress control circuit associated with the one or more ingress domains may distribute packet data of the one or more packets to the sub-crossbar domains. An egress control circuit of the apparatus receives data bits associated with the packet data from egresses associated with the plurality of sub-crossbar domains. The egress control circuit may reorder or refrain from reordering the data bits based on an attribute associated with the distribution of the packet data.