利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.018 seconds)

    Cache stashing system
    2.
    发明申请
    Cache stashing system 有权

    公开(公告)号：US20210397560A1

    公开(公告)日：2021-12-23

    申请号：US16907347

    申请日：2020-06-22

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Hillel Chapman ,  Mark B. Rosenbluth

    IPC: G06F12/0891 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/54 ,  H04L29/08 ,  H04L29/06

    Abstract: In one embodiment, a computer server system includes a memory to store data across memory locations, multiple processing cores including respective local caches in which to cache cache-lines read from the memory, an interconnect to manage read and write operations of the memory and local caches, maintain local cache location data of the cached cache-lines according to respective ones of the memory locations from which the cached cache-lines were read from the memory, receive a write request for a data element to be written to one of the memory locations, find a local cache location in which to write the data element responsively to the local cache location data and the memory location of the write request, and send an update request to a first processing core to update a respective first local cache with the data element responsively to the found local cache location.

    HANDLING TRANSPORT LAYER OPERATIONS RECEIVED OUT OF ORDER
    3.
    发明申请
    HANDLING TRANSPORT LAYER OPERATIONS RECEIVED OUT OF ORDER 审中-公开
    处理运输层操作接收订单

    公开(公告)号：US20150172226A1

    公开(公告)日：2015-06-18

    申请号：US14132014

    申请日：2013-12-18

    Applicant: Mellanox Technologies Ltd.

    Inventor： Idan Borshteen ,  Michael Kagan ,  Noam Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Dror Bohrer ,  Diego Crupnicoff

    IPC: H04L12/861 ,  H04L12/879

    CPC classification number: H04L49/9057 ,  G06F15/17331 ,  H04L49/901 ,  H04L67/1097

    Abstract: A method for communication includes receiving at a receiving node over a network from a sending node a succession of data packets belonging to a sequence of transactions, including at least one or more first packets belonging to a first transaction and one or more second packets belonging to a second transaction executed by the sending node after the first transaction, wherein at least one of the second packets is received at the receiving node before at least one of the first packets. At the receiving node, upon receipt of the data packets, data are written from the data packets in the succession to respective locations in a buffer. Execution of the second transaction at the receiving node is delayed until all of the first packets have been received and the first transaction has been executed at the receiving node.

    Abstract translation: 一种用于通信的方法包括在接收节点通过网络从发送节点接收属于事务序列的一系列数据分组，包括属于第一事务的至少一个或多个第一分组和属于第一事务的一个或多个第二分组 在所述第一事务之后由所述发送节点执行的第二事务，其中在所述第一分组中的至少一个之前在所述接收节点处接收所述第二分组中的至少一个。 在接收节点，在接收到数据分组时，将数据从连续的数据分组写入缓冲器中的相应位置。 在接收节点处的第二事务的执行被延迟，直到已经接收到所有第一个分组并且已经在接收节点处执行了第一个事务。

    CROSS-CHANNEL NETWORK OPERATION OFFLOADING FOR COLLECTIVE OPERATIONS
    4.
    发明申请
    CROSS-CHANNEL NETWORK OPERATION OFFLOADING FOR COLLECTIVE OPERATIONS 有权
    跨渠道网络操作卸载集合操作

    公开(公告)号：US20140324939A1

    公开(公告)日：2014-10-30

    申请号：US14324246

    申请日：2014-07-07

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Ishai Rabinobitz ,  Pavel Shamis ,  Gilad Shainer

    IPC: H04L29/08

    CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

    Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求 这取决于一个或多个其他工作队列的完成状态，以便执行操作。

    EDRAM refresh apparatus and method
    6.
    发明授权
    EDRAM refresh apparatus and method 有权

    公开(公告)号：US10998032B2

    公开(公告)日：2021-05-04

    申请号：US16268507

    申请日：2019-02-06

    Applicant: Mellanox Technologies, Ltd.

    Inventor： George Elias ,  Hillel Chapman ,  Eitan Zahavi ,  Elad Mentovich

    IPC: G11C11/406

    Abstract: One or more blocks of dynamic random access memory are embedded together with a processor and a data bus on an integrated circuit. The data bus has a bandwidth b for general operation including memory access, the block of dynamic random access memory further requiring data refresh at a refresh rate r. The block thus forms an eDRAM on the integrated circuit, typically an ASIC. A refresh controller embedded with the eDRAM may control refresh by clocking the data bus at a rate higher than the rate of the data bus to accommodate both the required memory access and the required data refresh.

    Maintaining packet order in offload of packet processing functions
    7.
    发明申请
    Maintaining packet order in offload of packet processing functions 审中-公开

    公开(公告)号：US20190081904A1

    公开(公告)日：2019-03-14

    申请号：US15701459

    申请日：2017-09-12

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dror Bohrer ,  Noam Bloch ,  Lior Narkis ,  Hillel Chapman ,  Gilad Hammer

    IPC: H04L12/863 ,  H04L12/813 ,  G06F9/455

    CPC classification number: H04L47/6235 ,  G06F9/45558 ,  G06F2009/45595 ,  H04L45/74 ,  H04L47/20 ,  H04L49/70

    Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.

    Cross-channel network operation offloading for collective operations
    8.
    发明授权
    Cross-channel network operation offloading for collective operations 有权
    跨渠道网络运营卸载集体运营

    公开(公告)号：US09344490B2

    公开(公告)日：2016-05-17

    申请号：US14324246

    申请日：2014-07-07

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Ishai Rabinobitz ,  Pavel Shamis ,  Gilad Shainer

    IPC: G06F9/54 ,  H04L29/08

    CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

    Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求 这取决于一个或多个其他工作队列的完成状态，以便执行操作。

    NETWORK OPERATION OFFLOADING FOR COLLECTIVE OPERATIONS
    9.
    发明申请
    NETWORK OPERATION OFFLOADING FOR COLLECTIVE OPERATIONS 审中-公开
    网络操作卸载集合操作

    公开(公告)号：US20160065659A1

    公开(公告)日：2016-03-03

    申请号：US14937907

    申请日：2015-11-11

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shahar ,  Hillel Chapman ,  Gilad Shainer ,  Adi Menachem ,  Ofer Hayut

    IPC: H04L29/08

    CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

    Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主处理器接收从要由该节点执行的操作导出的一个或多个工作请求。 NI维护多个工作队列，用于通过网络向一个或多个对等节点执行传输信道。 NI还包括控制电路，其被配置为通过主机接口接受工作请求，并且通过根据前进条件控制至少给定的工作队列的进度来执行工作请求，所述进展条件取决于 一个或多个其他工作队列的完成状态，以便执行操作。

    METHODS AND SYSTEMS FOR POLLING MEMORY OUTSIDE A PROCESSOR THREAD
    10.
    发明申请
    METHODS AND SYSTEMS FOR POLLING MEMORY OUTSIDE A PROCESSOR THREAD 审中-公开
    用于在处理器螺纹外部检测存储器的方法和系统

    公开(公告)号：US20140129784A1

    公开(公告)日：2014-05-08

    申请号：US13671475

    申请日：2012-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Hillel Chapman ,  Dror Goldenberg

    IPC: G06F12/00

    CPC classification number: G06F1/329 ,  G06F9/485 ,  G06F9/542 ,  G06F12/0815 ,  Y02D10/24

    Abstract: A system and method of monitoring a memory address is disclosed which may replace a polling operation on a memory by determining a memory address to monitor, notifying a cache controller of the memory address, and cause execution on a polling thread to wait. The cache controller may then monitor the memory address and notify the processor to resume execution of the thread. While the processor is waiting to be notified, it may enter a power save state or allow more time to be allocated to other threads being executed.

    Abstract translation: 公开了一种监视存储器地址的系统和方法，其可以通过确定存储器地址来代替存储器上的轮询操作，通知高速缓存控制器存储器地址，并使轮询线程上的执行等待。 然后，高速缓存控制器可以监视存储器地址并通知处理器恢复线程的执行。 当处理器等待通知时，它可能进入省电状态，或允许更多的时间被分配给正在执行的其他线程。

Patent Agency Ranking