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公开(公告)号：US08897324B2
公开(公告)日：2014-11-25
申请号：US13753399
申请日：2013-01-29
Applicant: Microchip Technology Incorporated
Inventor： Stephen Bowling , Brant Ivey
Abstract: A microcontroller has a timebase driven by a clock signal, wherein the timebase has a reset input and an output coupled with a comparator. The comparator is further coupled with a register and is operable to generate a synchronization output signal if the timebase matches the register value. The microcontroller further has a first multiplexer receiving the synchronization output signal from the comparator and further receiving at least one event signal generated by a unit other than the timebase, wherein the first multiplexer is operable to select either the synchronization output signal or the at least one event signal as a timebase synchronization output signal.
Abstract translation: 微控制器具有由时钟信号驱动的时基，其中时基具有复位输入和与比较器耦合的输出。 比较器还与寄存器耦合，如果时基匹配寄存器值，则可操作以产生同步输出信号。 微控制器还具有接收来自比较器的同步输出信号的第一多路复用器，并且还接收由除时基之外的单元产生的至少一个事件信号，其中第一多路复用器可操作以选择同步输出信号或至少一个 事件信号作为时基同步输出信号。
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公开(公告)号：US20160371220A1
公开(公告)日：2016-12-22
申请号：US15185257
申请日：2016-06-17
Applicant: Microchip Technology Incorporated
Inventor： Roshan Samuel , Janmichael Aberouette , Ward Brown , Chintan Desai , Brant Ivey , Razvan Dochia
CPC classification number: G06F13/426 , G06F13/385 , G06F13/4295
Abstract: A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.
Abstract translation: 公开了一种通用异步收发器（UART）接口。 UART接口可以包括可配置的异步接收器和发射器单元; 以及可配置状态机，其中所述状态机允许所述接收器和发射器单元的配置以支持各种波特率并提供起始位和停止位配置，其中所述状态机还可配置为自动支持多个通信协议。
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公开(公告)号：US10331610B2
公开(公告)日：2019-06-25
申请号：US15185257
申请日：2016-06-17
Applicant: Microchip Technology Incorporated
Inventor： Roshan Samuel , Janmichael Aberouette , Ward Brown , Chintan Desai , Brant Ivey , Razvan Dochia
Abstract: A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.
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Patent Agency Ranking
公开(公告)号：US10248521B2
公开(公告)日：2019-04-02
申请号：US15089352
申请日：2016-04-01
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , Brant Ivey , Sankar Rangarajan
IPC: G06F11/00 , G06F11/263 , G06F11/10 , G06F11/22
Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.
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公开(公告)号：US20140281465A1
公开(公告)日：2014-09-18
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
IPC: G06F9/44
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
Abstract translation: 公开了一种具有双引导功能的中央处理单元，包括指令存储器，进一步包括被配置为可单独编程的第一和第二存储器区域，其中第一和第二存储器区域可被分配给执行指令的有效存储器， 不活动内存。 用于中央处理单元的指令集包括允许执行从活动存储器区域到非活动存储器区域的交换的专用指令，其中通过在活动存储器中执行专用指令执行交换，随后进行程序流程改变 指令在活动存储器中，因此非活动存储器变为新的活动存储器，并且活动存储器变为新的非活动存储器，并且新的活动存储器中的指令的执行继续。
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公开(公告)号：US09858083B2
公开(公告)日：2018-01-02
申请号：US14204208
申请日：2014-03-11
Applicant: Microchip Technology Incorporated
Inventor： Michael I. Catherwood , Brant Ivey , Igor Wojewoda , David Mickey , Joseph Kanellopoulos
CPC classification number: G06F9/4401 , G06F8/656 , G06F9/441
Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.
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公开(公告)号：US20160292059A1
公开(公告)日：2016-10-06
申请号：US15089352
申请日：2016-04-01
Applicant: Microchip Technology Incorporated
Inventor： Michael Catherwood , Brant Ivey , Sankar Rangarajan
IPC: G06F11/263 , G06F11/10 , G06F11/22
CPC classification number: G06F11/263 , G06F11/10 , G06F11/2205 , G06F11/2215
Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.
Abstract translation: 公开了用于硬件验证的运行时纠错码（“ECC”）错误注入方案的系统和方法。 系统和方法包括配置读取路径以内部转发读取数据，以及经由读取故障注入逻辑将至少一个故障位注入转发的读取数据。 系统和方法还可以包括配置写入路径以内部转发写入数据，以及经由写入故障注入逻辑将至少一个故障位注入转发的写入数据。
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公开(公告)号：US20130195124A1
公开(公告)日：2013-08-01
申请号：US13753399
申请日：2013-01-29
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： Stephen Bowling , Brant Ivey
IPC: H04J3/06
Abstract: A microcontroller has a timebase driven by a clock signal, wherein the timebase has a reset input and an output coupled with a comparator. The comparator is further coupled with a register and is operable to generate a synchronization output signal if the timebase matches the register value. The microcontroller further has a first multiplexer receiving the synchronization output signal from the comparator and further receiving at least one event signal generated by a unit other than the timebase, wherein the first multiplexer is operable to select either the synchronization output signal or the at least one event signal as a timebase synchronization output signal.
Abstract translation: 微控制器具有由时钟信号驱动的时基，其中时基具有复位输入和与比较器耦合的输出。 比较器还与寄存器耦合，如果时基匹配寄存器值，则可操作以产生同步输出信号。 微控制器还具有接收来自比较器的同步输出信号的第一多路复用器，并且还接收由除时基之外的单元产生的至少一个事件信号，其中第一多路复用器可操作以选择同步输出信号或至少一个 事件信号作为时基同步输出信号。
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