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公开(公告)号：US20180137921A1
公开(公告)日：2018-05-17
申请号：US15869501
申请日：2018-01-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.
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公开(公告)号：US08799725B2
公开(公告)日：2014-08-05
申请号：US14034159
申请日：2013-09-23
Applicant: Micron Technology, Inc.
Inventor： Frankie F. Roohparvar , Benjamin Louie
Abstract: Methods of performing an internal diagnostic for a NAND configured memory device include storing data in a data cache coupled to an array of memory cells arranged in a NAND configuration, wherein the data stored in the data cache corresponds to at least one diagnostic function; performing a decode operation on the data stored in the data cache, wherein the decode operation generates a diagnostic function command for testing internal functions of the NAND configured memory device; and providing the decoded diagnostic function command to a state machine of the NAND configured memory device adapted to perform the decoded diagnostic function command.
Abstract translation: 执行NAND配置的存储器件的内部诊断的方法包括将数据存储在耦合到排列在NAND配置中的存储器单元阵列的数据高速缓存器中，其中存储在数据高速缓冲存储器中的数据对应于至少一个诊断功能; 对存储在数据高速缓存中的数据执行解码操作，其中解码操作产生用于测试NAND配置的存储器件的内部功能的诊断功能命令; 以及将解码的诊断功能命令提供给适于执行解码的诊断功能命令的NAND配置存储器件的状态机。
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公开(公告)号：US20170076806A1
公开(公告)日：2017-03-16
申请号：US15342255
申请日：2016-11-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
Abstract translation: 存储器设备被配置为存储在对存储器设备中的特定行存储器单元执行的存储器件操作期间要应用的许多访问线偏置模式。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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公开(公告)号：US09875802B2
公开(公告)日：2018-01-23
申请号：US15342255
申请日：2016-11-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
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公开(公告)号：US09218884B2
公开(公告)日：2015-12-22
申请号：US14153590
申请日：2014-01-13
Applicant: Micron Technology, Inc.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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Patent Agency Ranking
公开(公告)号：US09514829B2
公开(公告)日：2016-12-06
申请号：US14958217
申请日：2015-12-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
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公开(公告)号：US08543874B2
公开(公告)日：2013-09-24
申请号：US13651931
申请日：2012-10-15
Applicant: Micron Technology, Inc.
Inventor： Frankie F. Roohparvar , Benjamin Louie
IPC: G11C29/00
Abstract: Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device. Decode blocks adapted to interpret instructions and data stored in the memory device. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
Abstract translation: 利用存储在存储器件的存储器阵列中的指令来执行存储器件的内部操作的方法和装置。 解码块，适于解释存储在存储设备中的指令和数据。 通过执行存储在执行自检操作的存储器件的存储器阵列中的测试程序，可以使用方法来执行存储器件的内部自检操作。
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公开(公告)号：US10332603B2
公开(公告)日：2019-06-25
申请号：US15869501
申请日：2018-01-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.
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公开(公告)号：US20160086672A1
公开(公告)日：2016-03-24
申请号：US14958217
申请日：2015-12-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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公开(公告)号：US20140126297A1
公开(公告)日：2014-05-08
申请号：US14153590
申请日：2014-01-13
Applicant: Micron Technology, Inc.
Inventor： Benjamin Louie , Ali Mohammadzadeh , Aaron S. Yip
IPC: G11C16/10
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
Abstract translation: 公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。 存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。 方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。
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