公开(公告)号：US20200051638A1

公开(公告)日：2020-02-13

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20180012660A1

公开(公告)日：2018-01-11

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/08 ,  H01L27/105 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09748265B1

公开(公告)日：2017-08-29

申请号：US15176072

申请日：2016-06-07

Applicant: Micron Technology, Inc.

Inventor： Changhyun Lee

IPC: H01L23/532 ,  H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11556 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.

公开(公告)号：US09728266B1

公开(公告)日：2017-08-08

申请号：US15205574

申请日：2016-07-08

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20220208261A1

公开(公告)日：2022-06-30

申请号：US17688983

申请日：2022-03-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

公开(公告)号：US20210125669A1

公开(公告)日：2021-04-29

申请号：US17080553

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US11615838B2

公开(公告)日：2023-03-28

申请号：US17688983

申请日：2022-03-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

公开(公告)号：US11295809B2

公开(公告)日：2022-04-05

申请号：US17074690

申请日：2020-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.

公开(公告)号：US20210035630A1

公开(公告)日：2021-02-04

申请号：US17074690

申请日：2020-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.

公开(公告)号：US10818357B2

公开(公告)日：2020-10-27

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.