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    COMMUNICATING DATA WITH STACKED MEMORY DIES
    3.
    发明申请
    COMMUNICATING DATA WITH STACKED MEMORY DIES 有权

    公开(公告)号：US20230004507A1

    公开(公告)日：2023-01-05

    申请号：US17864023

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

    IPC: G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C5/02 ,  G06F13/42 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

    Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

    APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITECTURES
    4.
    发明申请
    APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITECTURES 有权

    公开(公告)号：US20220187988A1

    公开(公告)日：2022-06-16

    申请号：US17645101

    申请日：2021-12-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean D. Gans ,  Shunichi Saito

    IPC: G06F3/06 ,  G06F12/10

    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

    APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENT OF A SEMICONDUCTOR DEVICE
    5.
    发明申请
    APPARATUSES AND METHODS FOR DUTY CYCLE ADJUSTMENT OF A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220149828A1

    公开(公告)日：2022-05-12

    申请号：US17501858

    申请日：2021-10-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean D. Gans

    IPC: H03K5/156 ,  G11C29/50 ,  G11C11/4076 ,  G11C7/22 ,  G11C8/18 ,  G11C7/00 ,  G11C29/02

    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

    APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS
    6.
    发明申请
    APPARATUSES AND METHODS FOR STORING AND WRITING MULTIPLE PARAMETER CODES FOR MEMORY OPERATING PARAMETERS 有权

    公开(公告)号：US20210287724A1

    公开(公告)日：2021-09-16

    申请号：US17301531

    申请日：2021-04-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean D. Gans ,  Daniel C. Skinner

    IPC: G11C7/10

    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

    PREFETCH MANAGEMENT FOR MEMORY
    7.
    发明申请
    PREFETCH MANAGEMENT FOR MEMORY 有权

    公开(公告)号：US20210255958A1

    公开(公告)日：2021-08-19

    申请号：US17183225

    申请日：2021-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F12/0862 ,  G06F13/20

    Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.

    Methods for row hammer mitigation and memory devices and systems employing the same
    8.
    发明授权
    Methods for row hammer mitigation and memory devices and systems employing the same 有权

    公开(公告)号：US11087819B2

    公开(公告)日：2021-08-10

    申请号：US16597694

    申请日：2019-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Timothy B. Cowles ,  Dean D. Gans ,  Jiyun Li ,  Nathaniel J. Meier ,  Randall J. Rooney

    IPC: G11C7/00 ,  G11C11/406

    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

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