公开(公告)号：US12249381B2

公开(公告)日：2025-03-11

申请号：US18117268

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Kitae Park

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.

公开(公告)号：US20220208274A1

公开(公告)日：2022-06-30

申请号：US17217014

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Shigekazu Yamada

IPC: G11C16/16 ,  G11C16/30

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first control gates for respective first memory cells of the first memory block; a second memory block including second control gates for respective second memory cells of the second memory block; first diffusion regions coupled to the first control gates; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second control gates; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.

公开(公告)号：US20230326532A1

公开(公告)日：2023-10-12

申请号：US18117268

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Kitae Park

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A memory device having a memory array with a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines and control logic coupled with the memory array. The control logic perform operations including: determining a metadata value characterizing a first read level voltage of a highest threshold voltage distribution of a subset of the plurality of memory cells, wherein the metadata value comprises at least one of a failed byte count or a failed bit count; adjusting, based on the metadata value, a second read level voltage for a second-highest threshold voltage distribution of the subset of the plurality of memory cells; and causing, to perform an initial calibrated read of the subset of the plurality of memory cells, the adjusted second read level voltage to be applied to a wordline of the plurality of wordlines to read the second-highest threshold voltage distribution.

公开(公告)号：US20240248637A1

公开(公告)日：2024-07-25

申请号：US18412010

申请日：2024-01-12

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Xiangyu Yang ,  Ching-Huang Lu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with control logic. The control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. The control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. The control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. The control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.

公开(公告)号：US20240242754A1

公开(公告)日：2024-07-18

申请号：US18402875

申请日：2024-01-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ching-Huang Lu ,  Go Shikata ,  Gangotree Chakma

IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4076 ,  G11C11/4096

Abstract: A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying a set of parameters related to the memory device, selecting, based on the set of parameters, a magnitude of a bias voltage to be applied to a global wordline during a read state transition of a block of the memory device from a transient state to a stable state, and causing the bias voltage to be applied to the global wordline.

公开(公告)号：US11664076B2

公开(公告)日：2023-05-30

申请号：US17217014

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Shigekazu Yamada

IPC: G11C11/56 ,  G11C16/16 ,  G11C16/30

CPC classification number: G11C16/16 ,  G11C16/30

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first word lines for respective first memory cells of the first memory block; a second memory block including second word lines for respective second memory cells of the second memory block; first diffusion regions coupled to the first word lines; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second word lines; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.