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公开(公告)号：US20230207033A1
公开(公告)日：2023-06-29
申请号：US17590679
申请日：2022-02-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Harish V. Gadamsetty
CPC classification number: G11C29/026 , G11C7/20 , G11C7/1039 , G11C8/06 , G11C29/789 , G11C2029/1802
Abstract: An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.
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公开(公告)号：US11942171B2
公开(公告)日：2024-03-26
申请号：US17590679
申请日：2022-02-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Harish V. Gadamsetty
CPC classification number: G11C29/026 , G11C7/1039 , G11C7/20 , G11C8/06 , G11C29/789 , G11C2029/1802
Abstract: An example method may be used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.
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公开(公告)号：US11670356B2
公开(公告)日：2023-06-06
申请号：US17305878
申请日：2021-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Harish V. Gadamsetty , Gary Howe , Dennis G. Montierth , Michael A. Shore , Jason M. Johnson
IPC: G11C11/406 , G11C11/408 , G11C29/44 , G11C29/00 , G11C29/12
CPC classification number: G11C11/40622 , G11C11/4085 , G11C11/4087 , G11C29/4401 , G11C29/787 , G11C2029/1202
Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).
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Patent Agency Ranking
公开(公告)号：US11551779B2
公开(公告)日：2023-01-10
申请号：US17240389
申请日：2021-04-26
Applicant: Micron Technology, Inc.
Inventor： Harish V. Gadamsetty
IPC: G11C29/44 , G11C29/00 , H03K19/20 , H03K19/173 , G11C11/4091
Abstract: An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.
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公开(公告)号：US11837316B1
公开(公告)日：2023-12-05
申请号：US17812139
申请日：2022-07-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Scott E. Smith , Harish V. Gadamsetty
CPC classification number: G11C7/08 , G11C7/1009 , G11C7/1039 , G11C7/1096
Abstract: An exemplary semiconductor device includes circuitry to implement data mask operations by sending bit-specific, write enable signals (WREN) to control connection of a main or global data line to local data lines during a write operation. For example, a plurality of even sense amplifier stripes each receive a first set of WREN signals to control a corresponding passgate responsible for coupling one global data line to one local data line and a plurality of odd sense amplifier stripes each receive a second set of WREN signals to control a corresponding passgate responsible for coupling one global data line to one local data line.
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公开(公告)号：US20230020753A1
公开(公告)日：2023-01-19
申请号：US17305878
申请日：2021-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Harish V. Gadamsetty , Gary Howe , Dennis G. Montierth , Michael A. Shore , Jason M. Johnson
IPC: G11C11/406 , G11C11/408 , G11C29/00 , G11C29/44
Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).
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公开(公告)号：US20220343993A1
公开(公告)日：2022-10-27
申请号：US17240389
申请日：2021-04-26
Applicant: Micron Technology, Inc.
Inventor： Harish V. Gadamsetty
IPC: G11C29/44 , G11C29/00 , G11C7/06 , H03K19/173 , H03K19/20
Abstract: An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.
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公开(公告)号：US11232830B1
公开(公告)日：2022-01-25
申请号：US17119226
申请日：2020-12-11
Applicant: Micron Technology, Inc.
Inventor： Kallol Mazumder , Harish V. Gadamsetty
IPC: G11C7/00 , G11C11/4091 , G11C8/18 , G11C11/4076 , G11C11/4093
Abstract: Devices and methods include a command interface configured to receive commands, such as a write with an automatic precharge. A bank-specific decoder decodes the write with an automatic precharge command for a corresponding memory bank and outputs a write auto-precharge (WrAP) signal. This WrAP signal has not been adjusted for a write recovery time for the memory bank. Accordingly, bank processing circuitry in a bank receiving the WrAP signal uses the WrAP to cause its internal lockout circuitry to apply a tWR lockout based at least in part on a mode register setting and on the WrAP signal indicating receipt of the write with an automatic precharge command.
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