公开(公告)号：US11955160B2

公开(公告)日：2024-04-09

申请号：US17846967

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Fujiwara ,  Kevin G. Werhane ,  Jason M. Johnson ,  Daniel S. Miller

IPC: H03K5/133 ,  G11C11/4076 ,  G11C29/54

CPC classification number: G11C11/4076 ,  G11C29/54 ,  H03K5/133

Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.

公开(公告)号：US11508453B2

公开(公告)日：2022-11-22

申请号：US16996120

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson

IPC: G11C29/38 ,  G01R31/317 ,  G06F11/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091

Abstract: Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.

公开(公告)号：US11200939B1

公开(公告)日：2021-12-14

申请号：US16921729

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/40 ,  G11C11/406 ,  G06F11/30

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：US20210183461A1

公开(公告)日：2021-06-17

申请号：US16716366

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson

IPC: G11C29/38 ,  G11C29/44

Abstract: Methods, systems, and devices for data compression for global column repair are described. In some cases, a testing device may perform a first internal read operation to identify errors associated with on one or more column planes. A value (e.g., a bit) indicating whether an error occurred when testing each column plane may be stored. The testing device may perform a second internal read operation on the same column planes, or on column planes of a different bank of memory cells. The values (e.g., bits) indicating whether errors occurred during the first internal read operation and the values indicating whether errors occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair the defective column planes.

公开(公告)号：US10923172B2

公开(公告)日：2021-02-16

申请号：US16812854

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Christopher G. Wieduwilt ,  Daniel S. Miller ,  Yoshinori S. Fujiwara

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/4091 ,  G11C8/10 ,  G11C11/4074

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.

公开(公告)号：US10593392B1

公开(公告)日：2020-03-17

申请号：US16226525

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson ,  Christopher G. Wieduwilt ,  Daniel S. Miller ,  Yoshinori S. Fujiwara

IPC: G11C11/40 ,  G11C11/406 ,  G11C5/14 ,  G11C11/4091 ,  G11C8/10 ,  G11C11/4074

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.

公开(公告)号：US20230420030A1

公开(公告)日：2023-12-28

申请号：US17846967

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Yoshinori Fujiwara ,  Kevin G. Werhane ,  Jason M. Johnson ,  Daniel S. Miller

IPC: G11C11/4076 ,  H03K5/133 ,  G11C29/54

CPC classification number: G11C11/4076 ,  H03K5/133 ,  G11C29/54

Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.

公开(公告)号：US20220059177A1

公开(公告)日：2022-02-24

申请号：US16996120

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Jason M. Johnson

IPC: G11C29/38 ,  G01R31/317 ,  G06F11/10

Abstract: Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.

公开(公告)号：US20220005523A1

公开(公告)日：2022-01-06

申请号：US16921729

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Jason M. Johnson ,  Joo-Sang Lee

IPC: G11C11/406 ,  G06F11/30

Abstract: Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

公开(公告)号：US10930327B1

公开(公告)日：2021-02-23

申请号：US16773824

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Dave Jefferson ,  C. Omar Benitez ,  Yoshinori Fujiwara ,  Christopher S. Wieduwilt ,  Vivek Kotti ,  Dennis G. Montierth ,  Joshua E. Alzheimer ,  Daniel S. Miller ,  Kevin G. Werhane ,  Jason M. Johnson

IPC: G11C7/10 ,  G11C29/08 ,  G11C7/22 ,  G11C29/00

Abstract: Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.