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    Systems and methods for controlling semiconductor device wear
    1.
    发明授权
    Systems and methods for controlling semiconductor device wear 有权

    公开(公告)号：US10447267B1

    公开(公告)日：2019-10-15

    申请号：US16105751

    申请日：2018-08-20

    Applicant: Micron Technology, Inc.

    Inventor： William C. Waldrop

    IPC: G11C19/00 ,  H03K19/003 ,  H03K19/20 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/406

    Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.

    Metastable resistant latch
    3.
    发明授权
    Metastable resistant latch 有权

    公开(公告)号：US11264078B2

    公开(公告)日：2022-03-01

    申请号：US16781763

    申请日：2020-02-04

    Applicant: Micron Technology, inc.

    Inventor： Daniel B. Penney ,  William C. Waldrop

    IPC: G11C11/40 ,  G11C11/4076 ,  H03K19/20 ,  H03K3/037

    Abstract: Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT
    4.
    发明申请
    APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER CIRCUIT 有权

    公开(公告)号：US20250095713A1

    公开(公告)日：2025-03-20

    申请号：US18958966

    申请日：2024-11-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

    IPC: G11C11/4076 ,  G11C11/4096

    Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

    PARALLEL ERROR CALCULATION
    7.
    发明申请
    PARALLEL ERROR CALCULATION 审中-公开

    公开(公告)号：US20200057688A1

    公开(公告)日：2020-02-20

    申请号：US16105338

    申请日：2018-08-20

    Applicant: Micron Technology, Inc.

    Inventor： William C. Waldrop

    IPC: G06F11/07 ,  H03K21/38

    Abstract: Devices and methods for error checking transmissions include using error checking circuitry configured to receive a clock and reset. The error checking circuitry includes an input counter that is configured to receive the clock and to count out multiple input clocks from the received clock. The error checking circuitry also includes a delay model that is configured to receive the clock and to output a delayed clock. Also, the error checking circuitry includes an output counter that is configured to receive the delayed clock and to count out multiple output clocks from the received delayed clock. Furthermore, the error checking circuitry includes multiple error calculation circuits arranged in parallel that each are configured to: receive data based on a respective input clock, generate an error indicator based on the received data with the error indicator indicating whether an error exists in the received data, and output the error indicator based at least in part on a respective output clock.

    Reduced shifter memory system
    8.
    发明授权
    Reduced shifter memory system 有权

    公开(公告)号：US10354717B1

    公开(公告)日：2019-07-16

    申请号：US15976698

    申请日：2018-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Jason M. Brown ,  Vijayakrishna J. Vankayala ,  William C. Waldrop ,  Kallol Mazumder ,  Byung S. Moon ,  Ravi Kiran Kandikonda

    IPC: G11C11/4076 ,  G11C11/4093 ,  G06F11/10 ,  G11C11/4096

    Abstract: Aspects of the present disclosure eliminating the need for a memory device to have both a shifter that shifts input pin values from an input domain into a parity domain and another shifter that shifts a decoded command from the input domain into the parity domain. A memory device can achieve this by, when parity is being performed, shifting the input from the input pins into the parity domain prior to decoding the command. Using a multiplexer, the decoder can receive the command pin portion of the shifted input when parity checking is being performed and can receive the un-shifted command pin input when parity checking is not being performed. The decoder can use the command pin portion of the shifted input to generate shifted and decoded commands or can use the un-shifted command pin input to generate decoded commands.

    SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION
    9.
    发明申请
    SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION 审中-公开

    公开(公告)号：US20190122742A1

    公开(公告)日：2019-04-25

    申请号：US16049411

    申请日：2018-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Daniel B. Penney ,  William C. Waldrop

    IPC: G11C17/18 ,  G11C17/16 ,  H04L9/08 ,  G11C17/08

    Abstract: A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

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