-
公开(公告)号：US09177662B1
公开(公告)日：2015-11-03
申请号：US14481953
申请日：2014-09-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wen-Wei Yeh , Chih-Shen Chang , Kuo-Pin Chang
CPC classification number: G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/10
Abstract: A pre-reading method and a programming method for a 3D NAND flash memory are provided. The pre-reading method comprises the following steps. A selected string includes a first memory cell, two second memory cells and a plurality of third memory cells. The two second memory cells are adjacent to the first memory cell. The third memory cells are not adjacent to the first memory cell. A first pass voltage is applied on the second memory cells, a second pass voltage is applied on the third memory cells, and a read voltage is applied on the first memory cell via a plurality of word lines for reading a data of the first memory cell. The first pass voltage is larger than the second pass voltage.
Abstract translation: 提供了一种用于3D NAND闪存的预读方法和编程方法。 预读方法包括以下步骤。 所选择的串包括第一存储器单元，两个第二存储器单元和多个第三存储器单元。 两个第二存储单元与第一存储单元相邻。 第三存储单元不与第一存储单元相邻。 对第二存储单元施加第一通过电压，在第三存储单元施加第二通过电压，并且经由用于读取第一存储单元的数据的多条字线将读取电压施加在第一存储单元上 。 第一通过电压大于第二通过电压。
-
公开(公告)号：US09171636B2
公开(公告)日：2015-10-27
申请号：US13940010
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Kuo-Pin Chang , Wen-Wei Yeh , Chih-Shen Chang , Hang-Ting Lue
CPC classification number: G11C16/3459 , G11C16/3427
Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.
Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。
-
Patent Agency Ranking
公开(公告)号：US20160035424A1
公开(公告)日：2016-02-04
申请号：US14446866
申请日：2014-07-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo Pin Chang , Chih-Shen Chang , Hang-Ting Lue
CPC classification number: G11C16/10 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C29/024 , G11C29/028
Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
-
4.发明申请公开(公告)号：US20160012905A1
公开(公告)日：2016-01-14
申请号：US14326212
申请日：2014-07-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang , Chih-Shen Chang
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C2211/5622 , G11C2211/5648
Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.
Abstract translation: 编程具有交替页面取向的3D NAND闪存的常见问题包括背景图案效果和图案引起的程序干扰。 改进的编程技术可以显着地减少这些问题，并且在设置存储器单元的阈值电压时又提高精度。 提供了组合“逐字线”编程和“逐页”编程的方面的示例性技术。 这样，每个页面可以从最接近字符串选择结构的存储器单元开始编程，并且可以基本上同时编程多个偶数页或奇数页上的存储器单元。
-
公开(公告)号：US09373409B2
公开(公告)日：2016-06-21
申请号：US14326212
申请日：2014-07-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo-Pin Chang , Chih-Shen Chang
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C2211/5622 , G11C2211/5648
Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.
Abstract translation: 编程具有交替页面取向的3D NAND闪存的常见问题包括背景图案效果和图案引起的程序干扰。 改进的编程技术可以显着地减少这些问题，并且在设置存储器单元的阈值电压时又提高精度。 提供了组合“逐字线”编程和“逐页”编程的方面的示例性技术。 这样，每个页面可以从最接近字符串选择结构的存储器单元开始编程，并且可以基本上同时编程多个偶数页或奇数页上的存储器单元。
-
6.发明授权公开(公告)号：US09324437B2
公开(公告)日：2016-04-26
申请号：US14446866
申请日：2014-07-30
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuo Pin Chang , Chih-Shen Chang , Hang-Ting Lue
CPC classification number: G11C16/10 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C29/024 , G11C29/028
Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
Abstract translation: 3D NAND闪存阵列内的控制晶体管和存储单元都可以使用相同的技术（如电荷俘获结构）来创建，以简化制造过程。 然而，与传统的基于栅极氧化物的控制晶体管相比，所得到的控制晶体管最初可能具有较高的阈值电压可变性。 提供了在阵列操作期间修整控制晶体管以提供增加的可靠性和性能的示例性技术。
-
公开(公告)号：US20140211563A1
公开(公告)日：2014-07-31
申请号：US13940010
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Kuo-Pin Chang , Wen-Wei Yeh , Chih-Shen Chang , Hang-Ting Lue
IPC: G11C16/34
CPC classification number: G11C16/3459 , G11C16/3427
Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.
Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
