公开(公告)号：US20120217620A1

公开(公告)日：2012-08-30

申请号：US13461848

申请日：2012-05-02

申请人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

发明人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

公开(公告)号：US20100155921A1

公开(公告)日：2010-06-24

申请号：US12636758

申请日：2009-12-13

申请人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

发明人： Makoto SAEN ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

IPC分类号： H01L23/52 ,  H01L25/065

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

公开(公告)号：US20100008058A1

公开(公告)日：2010-01-14

申请号：US12465764

申请日：2009-05-14

申请人： Makoto SAEN ,  Kenichi OSADA

发明人： Makoto SAEN ,  Kenichi OSADA

IPC分类号： H05K1/14

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Traffic between logic LSIs and memory is increasing year by year and there is demand for increase of capacity of communication between them and reduction of power consumption in the communication. Communication distances between LSIs can be reduced by stacking the LSIs. However, in a simple stack of logic LSIs and memory LSIs, it is difficult to ensure heat dissipation to cope with increasing heat densities and ensure transmission characteristics for fast communication with the outside of the stacked package. Also required is a connection topology that improves the performance of communication among the stacked LSIs while ensuring the versatility of the LSIs. An external-communication LSI, a memory LSI, and a logic LSI are stacked in this order in a semiconductor package and are interconnected by through silicon vias. Output terminals of multiple stacked LSIs are connected to an input terminal of a through silicon via of the stacked memory LSI and input terminals of multiple stacked LSIs are connected to an output terminal of a through silicon via of the stacked memory LSI, thereby directly connecting both of the external-communication LSI and the logic LSI to a wiring line of the memory LSI.

摘要翻译： 逻辑LSI与内存之间的通信量逐年增加，需要增加通信能力，减少通信中的功耗。 可以通过堆叠LSI来降低LSI之间的通信距离。 然而，在逻辑LSI和存储器LSI的简单堆叠中，难以确保散热以应对增加的热密度并确保与堆叠封装的外部快速通信的传输特性。 还需要一种连接拓扑结构，从而提高堆叠LSI之间的通信性能，同时确保LSI的通用性。 外部通信LSI，存储器LSI和逻辑LSI以这种顺序堆叠在半导体封装中，并且通过硅通孔互连。 多层堆叠LSI的输出端子连接到层叠存储器LSI的贯穿硅通孔的输入端子，多层堆叠LSI的输入端子连接到层叠存储器LSI的贯穿硅通孔的输出端子，从而直接连接两个 的外部通信LSI和逻辑LSI连接到存储器LSI的布线。