Abstract:
The present disclosure includes systems and techniques relating to calibrating I/Q mismatches in communication systems. In some implementations, a reference signal to be transmitted by a transmitter (Tx) is identified. A loopback signal corresponding to the reference signal is generated by passing the reference signal through the TX and a receiver (Rx). The loopback signal includes an additional signal that distinguishes an in-phase/quadrature (I/Q) mismatch caused by the Tx (Tx I/Q mismatch) from an I/Q mismatch caused by the Rx (RX I/Q mismatch). A set of Tx I/Q mismatch parameters and a set of Rx I/Q mismatch parameters are determined based on the reference signal and the loopback signal, using the additional signal. A Tx signal is calibrated based on the set of Tx I/Q mismatch parameters, while a Rx signal is calibrated based on the set of Rx I/Q mismatch parameters, independently from the calibrating the Tx signal.
Abstract translation:本公开包括与校准通信系统中的I / Q不匹配相关的系统和技术。 在一些实现中,识别由发射机(Tx)发射的参考信号。 通过将参考信号通过TX和接收器(Rx)来产生对应于参考信号的环回信号。 环回信号包括区分由Rx(Tx I / Q不匹配)引起的与Rx(RX I / Q不匹配)引起的I / Q失配的同相/正交(I / Q)失配的附加信号。 使用附加信号,基于参考信号和环回信号确定一组Tx I / Q失配参数和一组Rx I / Q失配参数。 Tx信号基于Tx I / Q失配参数的集合进行校准,而RX信号基于Rx I / Q失配参数的集合进行校准,独立于校准Tx信号。
Abstract:
Disclosed is a radio frequency (RF) communication circuit having an input for receiving an RF signal and providing independently gain controlled signal paths from the input. In a first signal path, the signal is amplified by a constant gain. In a second signal path, the signal is amplified by a constant gain and by a variable gain amplifier.
Abstract:
Systems and techniques relating to wireless communication devices and reconfigurable an integrated RF Front-End for dual-band WLAN transceivers include, according to an aspect, an integrated circuit chip comprising: radio frequency (RF) Front-End circuitry, wherein the RF Front-End circuitry comprises (i) an antenna input line configured to connect with one or more antennas of a wireless communication device, (ii) a transmitter input line, (ii) a first receiver output line, (iii) and a second receiver output line; harmonic trap circuitry coupled with the RF Front-End circuitry via the antenna input line, the harmonic trap circuitry being fully integrated on the integrated circuit chip.
Abstract:
The present disclosure includes systems and techniques relating to calibrating I/Q mismatches in communication systems. In some implementations, a reference signal to be transmitted by a transmitter (Tx) is identified. A loopback signal corresponding to the reference signal is generated by passing the reference signal through the TX and a receiver (Rx). The loopback signal includes an additional signal that distinguishes an in-phase/quadrature (I/Q) mismatch caused by the Tx (Tx I/Q mismatch) from an I/Q mismatch caused by the Rx (RX I/Q mismatch). A set of Tx I/Q mismatch parameters and a set of Rx I/Q mismatch parameters are determined based on the reference signal and the loopback signal, using the additional signal. A Tx signal is calibrated based on the set of Tx I/Q mismatch parameters, while a Rx signal is calibrated based on the set of Rx I/Q mismatch parameters, independently from the calibrating the Tx signal.
Abstract:
An apparatus comprises an amplifier and a pre-distortion circuit coupled to an input of the amplifier. A saturation value of an input signal corresponds to a maximum output power of an output signal of the amplifier. An input target value of the input signal is determined according to the saturation value. The input target value is determined by subtracting an offset from the saturation value or by multiplying a ratio by the saturation value. An average value or an RMS value of the input signal is controlled to be substantially equal to the input target value. A method comprises determining an input target value according to a saturation value, and controlling an input signal according to the input target value.
Abstract:
A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.
Abstract:
An apparatus includes first through fourth circuits. The first circuit determines a region of an input signal. The region is one of a plurality of regions. The second circuit generates a rotated input signal by rotating the input signal by a first angle according to the region. The third circuit phase shifts a carrier signal by a second angle according to the region. A fourth circuit amplifies the phase shifted carrier signal according to the rotated input signal. A method comprises determining a region according to a phase angle of an input signal, determining a rotation angle according to the region, generating a rotated carrier signal according to a carrier signal and the rotation angle, generating a rotated input signal according to the input signal and the negative of the rotation angle, and amplifying the rotated carrier signal according to the rotated input signal.
Abstract:
Systems and techniques relating to wireless communication devices and reconfigurable an integrated RF Front-End for dual-band WLAN transceivers include, according to an aspect, an integrated circuit chip comprising: radio frequency (RF) Front-End circuitry, wherein the RF Front-End circuitry comprises (i) an antenna input line configured to connect with one or more antennas of a wireless communication device, (ii) a transmitter input line, (ii) a first receiver output line, (iii) and a second receiver output line; harmonic trap circuitry coupled with the RF Front-End circuitry via the antenna input line, the harmonic trap circuitry being fully integrated on the integrated circuit chip.
Abstract:
Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, an apparatus including: processor electronics; transceiver electronics coupled with the processor electronics, the transceiver electronics including modulation circuitry and a digital power amplifier coupled with the modulation circuitry; a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency; a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and one or more antennas coupled with the digital power amplifier in the transceiver electronics; wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.
Abstract:
Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, a device including: modulation circuitry of a radio frequency transmitter having a local oscillator frequency; a digital power amplifier coupled with the modulation circuitry; and a clock input coupled with the digital power amplifier; wherein the clock input provides a clock signal to the digital amplifier at a sampling clock frequency; and wherein the local oscillator frequency is an integer multiple of the sampling clock frequency.