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    Phase change memory with finite annular conductive path
    1.
    发明授权
    Phase change memory with finite annular conductive path 有权
    具有有限环形导电路径的相变存储器

    公开(公告)号：US07965537B2

    公开(公告)日：2011-06-21

    申请号：US12491816

    申请日：2009-06-25

    Applicant: Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC: G11C11/00

    CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  Y10T29/49002

    Abstract: A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.

    Abstract translation: 相变存储器件及其编程方法。 该方法包括确定相变存储器件中的存储器单元的最大可能电阻。 该方法包括确定相变存储器件中存储单元的高电阻状态。 该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。 该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。 在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

    Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
    4.
    发明授权
    Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 有权
    利用测量时间延迟作为电平定义的特征参数的多电平存储单元

    公开(公告)号：US07764533B2

    公开(公告)日：2010-07-27

    申请号：US11857321

    申请日：2007-09-18

    Applicant: Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Chung H. Lam ,  Bipin Rajendran

    IPC: G11C11/00

    CPC classification number: G11C13/0061 ,  G11C11/5628 ,  G11C11/565 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/32 ,  G11C2013/0054

    Abstract: A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.

    Abstract translation: 用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。 本发明的实施例需要接收读取存储在存储单元中的二进制值的请求。 预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。 然后激活电子电路中的字线。 放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。 此外，当字线被激活时，电子放电时间测量开始。 当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。 确定操作根据测量的电子放电时间确定二进制值。

    Phase change memory electrode with sheath for reduced programming current
    5.
    发明授权
    Phase change memory electrode with sheath for reduced programming current 有权
    具有护套的相变记忆电极，用于减少编程电流

    公开(公告)号：US08648326B2

    公开(公告)日：2014-02-11

    申请号：US13191490

    申请日：2011-07-27

    Applicant: Matthew J. Breitwisch ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Bipin Rajendran

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

    Abstract: An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.

    Abstract translation: 示例性实施例是相位存储单元，其包括底部触点和设置在底部触点上方的电绝缘层。 电绝缘层限定细长的通孔。 此外，底部电极至少部分地设置在通路中。 底部电极包括围绕第二导电材料的杆的第一导电材料的套筒。 第一导电材料和第二导电材料具有不同的比电阻。 存储单元还包括电耦合到第一电极的相变层。

    Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks
    6.
    发明授权
    Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
    将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统

    公开(公告)号：US08589320B2

    公开(公告)日：2013-11-19

    申请号：US13548532

    申请日：2012-07-13

    Applicant: Matthew J. Breitwisch ,  Chung Hon Lam ,  Dharmendra S. Modha ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Chung Hon Lam ,  Dharmendra S. Modha ,  Bipin Rajendran

    IPC: G06E1/00

    CPC classification number: G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  H01L27/285

    Abstract: A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.

    Abstract translation: 神经元系统包括电连接到多个神经元电路块的多个突触块。 多个突触块包括多个神经形态电路。 每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。 每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入 块。

    PHASE CHANGE MEMORY ELECTRODE WITH SHEATH FOR REDUCED PROGRAMMING CURRENT
    7.
    发明申请
    PHASE CHANGE MEMORY ELECTRODE WITH SHEATH FOR REDUCED PROGRAMMING CURRENT 有权
    相位改变记忆电极，减少编程电流

    公开(公告)号：US20130026436A1

    公开(公告)日：2013-01-31

    申请号：US13191490

    申请日：2011-07-27

    Applicant: Matthew J. Breitwisch ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Bipin Rajendran

    IPC: H01L47/00 ,  H01L21/20

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

    Abstract: An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.

    Abstract translation: 示例性实施例是相位存储单元，其包括底部触点和设置在底部触点上方的电绝缘层。 电绝缘层限定细长的通孔。 此外，底部电极至少部分地设置在通路中。 底部电极包括围绕第二导电材料的杆的第一导电材料的套筒。 第一导电材料和第二导电材料具有不同的比电阻。 存储单元还包括电耦合到第一电极的相变层。

    Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material
    8.
    发明授权
    Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material 有权
    使用场效应晶体管（FET）和可变电阻材料的区域效率的神经元电路

    公开(公告)号：US08311965B2

    公开(公告)日：2012-11-13

    申请号：US12620624

    申请日：2009-11-18

    Applicant: Matthew J. Breitwisch ,  Chung Hon Lam ,  Dharmendra S. Modha ,  Bipin Rajendran

    Inventor： Matthew J. Breitwisch ,  Chung Hon Lam ,  Dharmendra S. Modha ,  Bipin Rajendran

    IPC: G06F17/00

    CPC classification number: G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  H01L27/285

    Abstract: A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.

    Abstract translation: 神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。 神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。 神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。 神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点 神经元电路。

    THERMALLY INSULATED PHASE MATERIAL CELLS
    10.
    发明申请
    THERMALLY INSULATED PHASE MATERIAL CELLS 有权
    热绝缘相材料

    公开(公告)号：US20120129313A1

    公开(公告)日：2012-05-24

    申请号：US13363549

    申请日：2012-02-01

    Applicant: Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

    Inventor： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

    IPC: H01L21/62

    CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

    Abstract translation: 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。

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