公开(公告)号：US20230376671A1

公开(公告)日：2023-11-23

申请号：US18315712

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Jen-Wei Lee ,  Yi-Ying Liao ,  Te-Wei Chen ,  Yu-Hsiu Lin ,  Chia-Wei Chen ,  Chun-Ku Ting ,  Sheng-Tai Tseng ,  Ronald Kuo-Hua Ho ,  Hsin-Chuan Kuo ,  Chun-Chieh Wang ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Tai-Lai Tung ,  Da-Shan Shiu

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/20

Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

公开(公告)号：US09940422B2

公开(公告)日：2018-04-10

申请号：US14743099

申请日：2015-06-18

Applicant: MediaTek Inc.

Inventor： Chin-Hsiung Hsu ,  Chun-Chih Yang

IPC: G06F17/50 ,  H03K19/177

CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5054 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/08 ,  G06F2217/78 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/17796

Abstract: A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.

公开(公告)号：US09946829B2

公开(公告)日：2018-04-17

申请号：US14932165

申请日：2015-11-04

Applicant: MediaTek Inc.

Inventor： Shih-Ying Liu ,  Chin-Hsiung Hsu ,  Chi-Yuan Liu ,  Chun-Chih Yang ,  Chao-Neng Huang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.

公开(公告)号：US09892226B2

公开(公告)日：2018-02-13

申请号：US15147152

申请日：2016-05-05

Applicant: MediaTek Inc.

Inventor： Chin-Hsiung Hsu ,  Chun-Chih Yang ,  Shih-Ying Liu ,  Che-Jung Lou ,  Chao-Neng Huang ,  Chi-Yuan Liu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.

公开(公告)号：US20240311542A1

公开(公告)日：2024-09-19

申请号：US18396711

申请日：2023-12-27

Applicant: MEDIATEK INC.

Inventor： Jen-Wei Lee ,  Yi-Ying Liao ,  Te-Wei Chen ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Ronald Kuo-Hua Ho ,  Bo-Jiun Hsu ,  Wei-Hsien Lin ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Tai-Lai Tung

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

公开(公告)号：US10162927B2

公开(公告)日：2018-12-25

申请号：US15915172

申请日：2018-03-08

Applicant: MEDIATEK INC.

Inventor： Shih-Ying Liu ,  Chin-Hsiung Hsu ,  Chi-Yuan Liu ,  Chun-Chih Yang ,  Chao-Neng Huang

IPC: G06F17/50

Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.

公开(公告)号：US20230376653A1

公开(公告)日：2023-11-23

申请号：US18315904

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Hsin-Chuan Kuo ,  Chia-Wei Chen ,  Yu-Hsiu Lin ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Chun-Ku Ting ,  Fang-Ming Yang ,  Yu-Hsien Ku ,  Jen-Wei Lee ,  Ronald Kuo-Hua Ho ,  Chun-Chieh Wang ,  Yi-Ying Liao ,  Tai-Lai Tung ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Kun-Chin Huang

IPC: G06F30/27 ,  G06F30/392

CPC classification number: G06F30/27 ,  G06F30/392

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

公开(公告)号：US09817936B2

公开(公告)日：2017-11-14

申请号：US14741771

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Chin-Hsiung Hsu ,  Chun-Chih Yang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/08

Abstract: A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.