公开(公告)号：US09455037B2

公开(公告)日：2016-09-27

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C11/34 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

公开(公告)号：US20140254244A1

公开(公告)日：2014-09-11

申请号：US14199708

申请日：2014-03-06

Applicant: Microchip Technology Incorporated

Inventor： Traian Bontas ,  Claudiu-Dumitru Nechifor ,  Iulian Dumitru ,  Kent Hewitt

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C13/0007 ,  G11C13/0011 ,  G11C14/009 ,  G11C17/165 ,  G11C17/18

Abstract: By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and still have enough difference between their resistances to read the desired data state that was programmed. A pair of ReRAM or CBRAM resistive memory devices are configured as a one bit memory cell and used to store a single data bit wherein one of the resistive memory devices is in an ERASE condition and the other resistive memory devices of the pair is in a WRITE condition. Reading the resistance states of the resistive memory device pairs is accomplished without having to use a reference voltage or current since a trip-point is between the conductive states thereof.

Abstract translation: 通过将交叉耦合布置的导电和非导电电阻存储器单元布置成便于读取数据状态，存储器单元可以在其电阻值上具有非常小的差异并仍然正确读取。 这允许两个存储单元的电阻随时间变化，并且在它们的电阻之间仍然具有足够的差异以读取所编程的所需数据状态。 一对ReRAM或CBRAM电阻性存储器件被配置为一位存储器单元，并用于存储单个数据位，其中一个电阻存储器件处于擦除状态，并且该对中的另一个电阻存储器件处于写入 条件。 读取电阻式存储器件对的电阻状态是完成的，而不必使用参考电压或电流，因为跳变点在其导电状态之间。

公开(公告)号：US20200058355A1

公开(公告)日：2020-02-20

申请号：US16539766

申请日：2019-08-13

Applicant: Microchip Technology Incorporated

Inventor： Jen-I Pi ,  Kent Hewitt

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34

Abstract: A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.

公开(公告)号：US10910058B2

公开(公告)日：2021-02-02

申请号：US16539766

申请日：2019-08-13

Applicant: Microchip Technology Incorporated

Inventor： Jen-I Pi ,  Kent Hewitt

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

Abstract: A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.

公开(公告)号：US09343147B2

公开(公告)日：2016-05-17

申请号：US14199708

申请日：2014-03-06

Applicant: Microchip Technology Incorporated

Inventor： Traian Bontas ,  Claudiu-Dumitru Nechifor ,  Iulian Dumitru ,  Kent Hewitt

IPC: G11C7/02 ,  G11C11/00 ,  G11C13/00 ,  G11C7/06 ,  G11C14/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C13/0007 ,  G11C13/0011 ,  G11C14/009 ,  G11C17/165 ,  G11C17/18

Abstract: By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and still have enough difference between their resistances to read the desired data state that was programmed. A pair of ReRAM or CBRAM resistive memory devices are configured as a one bit memory cell and used to store a single data bit wherein one of the resistive memory devices is in an ERASE condition and the other resistive memory devices of the pair is in a WRITE condition. Reading the resistance states of the resistive memory device pairs is accomplished without having to use a reference voltage or current since a trip-point is between the conductive states thereof.

Abstract translation: 通过将交叉耦合布置的导电和非导电电阻存储器单元布置成便于读取数据状态，存储器单元可以在其电阻值上具有非常小的差异并仍然正确读取。 这允许两个存储单元的电阻随时间变化，并且在它们的电阻之间仍然具有足够的差异以读取所编程的所需数据状态。 一对ReRAM或CBRAM电阻性存储器件被配置为一位存储器单元，并用于存储单个数据位，其中一个电阻存储器件处于擦除状态，并且该对中的另一个电阻存储器件处于写入 条件。 读取电阻式存储器件对的电阻状态是完成的，而不必使用参考电压或电流，因为跳变点在其导电状态之间。

公开(公告)号：US20140269102A1

公开(公告)日：2014-09-18

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C16/10

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。