公开(公告)号：US10050131B2

公开(公告)日：2018-08-14

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US09455037B2

公开(公告)日：2016-09-27

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C11/34 ,  G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

公开(公告)号：US20170170303A1

公开(公告)日：2017-06-15

申请号：US15375094

申请日：2016-12-11

Applicant: Microchip Technology Incorporated

Inventor： Jack Wong ,  Sajid Kabeer ,  Mel Hymas ,  Santosh Murali ,  Brad Kopp

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

公开(公告)号：US20140269102A1

公开(公告)日：2014-09-18

申请号：US14209275

申请日：2014-03-13

Applicant: Microchip Technology Incorporated

Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

IPC: G11C16/10

CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。