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    MEMORY TIERING USING PCIe CONNECTED FAR MEMORY
    2.
    发明申请
    MEMORY TIERING USING PCIe CONNECTED FAR MEMORY 有权

    公开(公告)号：US20220283949A1

    公开(公告)日：2022-09-08

    申请号：US17824685

    申请日：2022-05-25

    Applicant: Micron Technology, Inc.

    Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

    IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

    Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

    Memory tiering using PCIe connected far memory
    3.
    发明授权
    Memory tiering using PCIe connected far memory 有权

    公开(公告)号：US11379373B2

    公开(公告)日：2022-07-05

    申请号：US16539139

    申请日：2019-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

    IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

    Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

    Cache operations in a hybrid dual in-line memory module
    4.
    发明授权
    Cache operations in a hybrid dual in-line memory module 有权

    公开(公告)号：US11169920B2

    公开(公告)日：2021-11-09

    申请号：US16573305

    申请日：2019-09-17

    Applicant: Micron Technology, Inc.

    Inventor： Paul Stonelake ,  Horia C. Simionescu ,  Samir Mittal ,  Robert M. Walker ,  Anirban Ray ,  Gurpreet Anand

    IPC: G06F12/0811 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0862

    Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

    ISOLATED PERFORMANCE DOMAINS IN A MEMORY SYSTEM
    5.
    发明申请
    ISOLATED PERFORMANCE DOMAINS IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200301848A1

    公开(公告)日：2020-09-24

    申请号：US16893757

    申请日：2020-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Anirban Ray ,  Parag R. Maharana

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F9/50 ,  G06F9/455 ,  G06F9/30

    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory allocation value in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context.

    OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS
    8.
    发明公开
    OPTIMIZATION OF DATA ACCESS AND COMMUNICATION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20230362280A1

    公开(公告)日：2023-11-09

    申请号：US18351991

    申请日：2023-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand

    IPC: H04L67/63 ,  G06F12/02 ,  G06F9/455 ,  H04L67/1097

    CPC classification number: H04L67/63 ,  G06F12/0246 ,  G06F9/45558 ,  H04L67/1097 ,  G06F2009/45583

    Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.

    CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE
    10.
    发明申请
    CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE 有权

    公开(公告)号：US20220027271A1

    公开(公告)日：2022-01-27

    申请号：US17450124

    申请日：2021-10-06

    Applicant: Micron Technology, Inc.

    Inventor： Paul Stonelake ,  Horia C. Simionescu ,  Samir Mittal ,  Robert W. Walker ,  Anirban Ray ,  Gurpreet Anand

    IPC: G06F12/0811 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0862

    Abstract: A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.

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