公开(公告)号：US09997220B2

公开(公告)日：2018-06-12

申请号：US15243651

申请日：2016-08-22

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US11087806B2

公开(公告)日：2021-08-10

申请号：US16000149

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US20180286470A1

公开(公告)日：2018-10-04

申请号：US16000149

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US20180053538A1

公开(公告)日：2018-02-22

申请号：US15243651

申请日：2016-08-22

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US20250140304A1

公开(公告)日：2025-05-01

申请号：US18774032

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Yukimi Morimoto ,  Takayuki Miyamoto ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.

公开(公告)号：US11062747B2

公开(公告)日：2021-07-13

申请号：US16143187

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: An example apparatus includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.

公开(公告)号：US20200098405A1

公开(公告)日：2020-03-26

申请号：US16143187

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.

公开(公告)号：US12183385B2

公开(公告)日：2024-12-31

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4096 ,  G11C11/4076

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20240062803A1

公开(公告)日：2024-02-22

申请号：US17890974

申请日：2022-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20190244644A1

公开(公告)日：2019-08-08

申请号：US15890943

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Yoshiya Komatsu ,  Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  H03L7/08

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.