公开(公告)号：US20240420746A1

公开(公告)日：2024-12-19

申请号：US18814826

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20210241810A1

公开(公告)日：2021-08-05

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US09196321B2

公开(公告)日：2015-11-24

申请号：US14045521

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Vijay Vankayala ,  Brian Gross ,  Gary Howe ,  Roy E. Greeff

IPC: G11C7/00 ,  G11C7/02 ,  G11C5/06 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract translation: 本文公开的装置和方法包括由存储管芯执行的装置和方法，其操作用于检测连接到存储管芯的总线上的命令是否响应于芯片选择信号寻址到另一存储器管芯，并且改变阻抗 存储器管芯的片上终端电路响应于检测。

公开(公告)号：US20150098285A1

公开(公告)日：2015-04-09

申请号：US14045521

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Vijay Vankayala ,  Brian Gross ,  Gary Howe ,  Roy E. Greeff

IPC: G11C7/02

CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105

Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.

Abstract translation: 本文公开的装置和方法包括由存储管芯执行的装置和方法，其操作用于检测连接到存储管芯的总线上的命令是否响应于芯片选择信号寻址到另一存储器管芯，并且改变阻抗 存储器管芯的片上终端电路响应于检测。

公开(公告)号：US12087394B2

公开(公告)日：2024-09-10

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US20240087621A1

公开(公告)日：2024-03-14

申请号：US17930655

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US11430504B2

公开(公告)日：2022-08-30

申请号：US17005034

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Miles S. Wiscombe ,  Scott E. Smith ,  Gary L. Howe ,  Brian W. Huber ,  Tony M. Brewer

IPC: G06F13/28 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406 ,  G11C11/4094

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

公开(公告)号：US11183980B1

公开(公告)日：2021-11-23

申请号：US16925590

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber

IPC: H03F3/45 ,  H03K3/037 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4076

Abstract: Techniques described herein are related to spread amplifier having a differential amplifier spread (DAS) configured to receive a pair of input signals and to provide a plurality of graded outputs each having different output levels. The spread amplifier further includes a final driver stage having a plurality of final drivers, wherein each of the final drivers is configured to receive a respective one of the plurality of graded outputs. The spread amplifier may be used for the regulation of various voltages such as VDQS and VARY.

公开(公告)号：US20230120654A1

公开(公告)日：2023-04-20

申请号：US18084135

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US11568913B2

公开(公告)日：2023-01-31

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.