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    CAPACITY EXPANSION FOR MEMORY SUB-SYSTEMS
    1.
    发明申请
    CAPACITY EXPANSION FOR MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20210132798A1

    公开(公告)日：2021-05-06

    申请号：US16672321

    申请日：2019-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.

    CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE
    2.
    发明申请
    CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE 有权

    公开(公告)号：US20210027812A1

    公开(公告)日：2021-01-28

    申请号：US16949036

    申请日：2020-10-09

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin ,  Ying Yu Tai ,  Samir Mittal

    IPC: G11C5/14 ,  G11C13/00 ,  G11C11/4074 ,  G06F3/06

    Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

    STRIPE MAPPING IN MEMORY
    3.
    发明申请
    STRIPE MAPPING IN MEMORY 审中-公开

    公开(公告)号：US20190324847A1

    公开(公告)日：2019-10-24

    申请号：US16458578

    申请日：2019-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin ,  Joseph M. Jeddeloh

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

    Capacity expansion for memory sub-system controllers having at least I/O expander circuit to limit impedance loads
    5.
    发明授权
    Capacity expansion for memory sub-system controllers having at least I/O expander circuit to limit impedance loads 有权

    公开(公告)号：US11573703B2

    公开(公告)日：2023-02-07

    申请号：US17445258

    申请日：2021-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin

    IPC: G06F3/00 ,  G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.

    CAPACITY EXPANSION FOR MEMORY SUB-SYSTEMS
    6.
    发明申请
    CAPACITY EXPANSION FOR MEMORY SUB-SYSTEMS 有权

    公开(公告)号：US20210373763A1

    公开(公告)日：2021-12-02

    申请号：US17445258

    申请日：2021-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.

    Stripe mapping in memory
    7.
    发明授权
    Stripe mapping in memory 有权

    公开(公告)号：US10339005B2

    公开(公告)日：2019-07-02

    申请号：US15689114

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin ,  Joseph M. Jeddeloh

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

    SCALABLE LOW-LATENCY STORAGE INTERFACE
    8.
    发明申请
    SCALABLE LOW-LATENCY STORAGE INTERFACE 审中-公开

    公开(公告)号：US20200081659A1

    公开(公告)日：2020-03-12

    申请号：US16681316

    申请日：2019-11-12

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin ,  Yves Tchapda ,  Stephen Marshall ,  Samuel Bradshaw ,  Niels Reimers

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

    Abstract: Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

    CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE
    9.
    发明申请
    CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE 审中-公开

    公开(公告)号：US20190333548A1

    公开(公告)日：2019-10-31

    申请号：US16226626

    申请日：2018-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin ,  Ying Yu Tai ,  Samir Mittal

    IPC: G11C5/14 ,  G11C13/00 ,  G11C11/4074 ,  G06F3/06

    Abstract: An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

    Capacity expansion channels for memory sub-systems
    10.
    发明授权
    Capacity expansion channels for memory sub-systems 有权

    公开(公告)号：US11119658B2

    公开(公告)日：2021-09-14

    申请号：US16672321

    申请日：2019-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Edward McGlaughlin

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.

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